The CDF silicon vertex trigger Page: 3 of 4
This article is part of the collection entitled: Office of Scientific & Technical Information Technical Reports and was provided to Digital Library by the UNT Libraries Government Documents Department.
The following text was automatically extracted from the image on this page using optical character recognition software:
and looser fiducial requirements reduce the effi-
ciency further; the ultimate denominator for SVT
would be all XFT-matched offline silicon tracks
that are useful for physics analysis.
SVT is a system of 150 custom 9U VME boards
containing FPGAs, RAMs, FIFOs, and one ASIC
design. CPUs are used only for initialization and
monitoring. SVT's input comprises 144 optical
fibers, 1 Gbit/s each, and one 0.2 Mbit/s LVDS
cable; its output is one 0.7 Mbit/s LVDS cable.
Three key features allow SVT to carry out in
15 ps a silicon track reconstruction that typically
requires 0(0.1 s) in software: a highly paral-
lel/pipelined architecture, custom VLSI pattern
recognition, and a linear track fit in fast FPGAs.
The silicon detector's modular, symmetric ge-
ometry lends itself to parallel processing. SVT's
first stage, converting a sparsified list of channel
numbers and pulse heights into charge-weighted
hit centroids, processes 12 x 6 x 5 (azimuthal x
longitudinal x radial) silicon planes in 360 iden-
tical FPGAs. The overall structure of SVT re-
flects the detector's 12-fold azimuthal symme-
try. Each 30 azimuthal slice is processed in its
own asynchronous, data-driven pipeline that first
computes hit centroids, then finds coincidences
to form track candidates, then fits the silicon hits
and drift chamber track for each candidate to ex-
tract circle parameters and a goodness of fit.
In SVT's usual configuration, a track candi-
date requires a coincidence of an XFT track and
hits in a specified four (out of five available) sili-
con layers. To define a coincidence, each detector
plane is divided into bins of programmable width,
typically 250-700 pm, and XFT tracks are swum
to the outer radius of the silicon detector and
binned with 3 mm typical width. For each 30
slice, the set of 32K most probable coincidences
("patterns") is computed offline in a Monte Carlo
program and loaded into 256 custom VLSI asso-
ciative memory (AM) chips. For every event, each
binned hit is presented in parallel to the 256 AM
chips, and the hit mask for each of the 128 pat-
terns per chip is accumulated in parallel. When
the last hit has been read, a priority encoder enu-
merates the patterns for which all five layers have
a matching hit. The processing time is thus lin-
ear in the total number of hits in each slice and
linear in the number of matched patterns.
There is no exact linear relationship between
the transverse parameters c, 0, d of a track in a
solenoidal field and the coordinates at which the
track meets a set of flat detector planes: the coor-
dinates are more closely linear in cos $, tan 0, and
S. But for pT > 2 GeV, Idl < 1 mm, 101 < 15 ,
a linear fit biases d by at most a few percent. By
linear regression to Monte Carlo data, we derive
the 3 x 6 coefficients V and 3 intercepts fo relating
p = (c, 0, d) to the vector f of cXFT, OXFT, and
four silicon hits: f = fo + V f x. The same regres-
sion produces coefficients C and intercepts xo,
corresponding to the fit's 3 degrees of freedom,
with which we calculate constraints ; = o+C C
and the usual X2 = 1i12. In the start-of-run down-
load, we precompute f and X for the coordinates
at the edge of each pattern and store them in flash
memory. Using each candidate's pattern ID as a
hint, the fitter board computes corrections to f
and X with respect to the pattern edge, using 8-
bit multiplication in 6 parallel FPGAs, in 250 ns
per fitted track. Tracks passing programmable
goodness-of-fit cuts propagate downstream.
3. SVT DIAGNOSTIC FEATURES
An SVT whose processing time, resolution, or
inefficiency were 20-30% larger would still have
enabled novel physics results at CDF. But an
SVT that could not be commissioned quickly or
operated reliably would have been a failure. Sev-
eral design features of SVT contributed to its
rapid commissioning and reliable operation.
The essence of SVT's component-based archi-
tecture is captured by the SVT cable and the SVT
Merger board. Nearly all SVT internal data-
hit centroids, drift chamber tracks, pattern IDs,
track candidates, and fitted SVT tracks-travel
as LVDS signals on common 26-conductor-pair
cables carrying data bits, a data strobe, a flow-
control signal, and a ground pair. The data are
variable-length packets of 21-bit words, plus end-
packet and end-event bits. Data fan-in and fan-
out are performed inside FPGAs, not on back-
planes, by a universal Merger board that con-
catenates event data for up to four SVT cable
inputs and provides two SVT cable outputs. Ev-
Here’s what’s next.
This article can be searched. Note: Results may vary based on the legibility of text within the document.
Tools / Downloads
Get a copy of this page or view the extracted text.
Citing and Sharing
Basic information for referencing this web page. We also provide extended guidance on usage rights, references, copying or embedding.
Reference the current page of this Article.
Ashmanskas, B.; Barchiesi, A. & Bardi, A. The CDF silicon vertex trigger, article, June 23, 2003; Batavia, Illinois. (digital.library.unt.edu/ark:/67531/metadc737597/m1/3/: accessed May 24, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.