A dedicated LHC collider Beauty experiment for precision measurements of CP-violation. LHC-B letter of intent Page: 4 of 6
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Figure 10.15: Energy [GeV] in the Electro-magnetic
and Hadron Calorimeters for single interactions (solid
line) and double interactions (dashed line)
crossings. The calorimeter-based triggers are espe-
cially sensitive to the presence of a second event in
the same bunch crossings. Therefore, our nominal
minimum-bias trigger rate of 230 KHz is most effec-
tive with the inclusion of a pile-up veto in the Level-1
For reasons given above, at least for the main ele-
ments of the LHC-B physics programme, the Level-1
trigger will include a pile-up rejection. The trigger ef-
ficiencies and the event yields given at the end of this
chapter include losses from the pile-up veto discussed
10.5 Level-1 hardware implementa-
From the descriptions of the various trigger algo-
rithms, it is clear that the corresponding hardware
should provide a high level of performance, both in
terms of speed and sophistication. The main ob-
stacles to be surmounted are the need to sustain a
40 MHz input rate in a pipelined mode with a rather
large amount of inter-communication between detec-
In view of the extremely critical role that the trig-
ger plays in LHC-B and of the natural expectation
that, at the time of running, unanticipated conditions
might have to be met, the chosen trigger hardware
should allow a good degree of flexibility and possibil-
Figure 10.16: Full "OR'ed" Level-i trigger rate
as a function of luminosity, including pile-up veto.
The dashed curve shows the component of the full
Level-1 trigger rate for bunches which contain single-
ity of expansion. Moreover, given the rapid advances
in the performance attainable from digital systems, it
is felt that, even for the handling of the calorimeter
information, a digital system is preferred to an ana-
logue one. Such requirements point to a choice of a
programmable, very high-performance system of par-
allel processors, capable of very fast data switching.
We wish to point out that a possible solution,
meeting all of the demanding requirements, could al-
ready be found within the realm of existing develop-
ments. As an "existence proof" we note that the sys-
tem called "3D-Flow", originally designed to provide
Level-1 triggering for the high-pt SSC detectors,
could satisfy these needs.
The "3D-Flow" consists essentially of a parallel-
processing architecture built around an ASIC con-
taining four identical processors. Each processor,
highly optimized for fast, parallel communication,
contains six communication channels, which can all
operate concurrently. In a typical application, an in-
dividual processor would be connected as sketched
in Fig. 10.17, where in the planar structures each
processor is associated directly with individual de-
tector elements or some set of them, and the stack of
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Crosetto, Dario B. A dedicated LHC collider Beauty experiment for precision measurements of CP-violation. LHC-B letter of intent, report, March 28, 1996; United States. (https://digital.library.unt.edu/ark:/67531/metadc724035/m1/4/: accessed June 19, 2019), University of North Texas Libraries, Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.