Instruction-Level Characterization of Scientific Computing Applications Using Hardware Performance Counters

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Workload characterization has been proven an essential tool to architecture design and performance evaluation in both scientific and commercial computing areas. Traditional workload characterization techniques include FLOPS rate, cache miss ratios, CPI (cycles per instruction or IPC, instructions per cycle) etc. With the complexity of sophisticated modern superscalar microprocessors, these traditional characterization techniques are not powerful enough to pinpoint the performance bottleneck of an application on a specific microprocessor. They are also incapable of immediately demonstrating the potential performance benefit of any architectural or functional improvement in a new processor design. To solve these problems, many people rely on simulators, ... continued below

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9 p.

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Luo, Y. & Cameron, K.W. November 24, 1998.

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Description

Workload characterization has been proven an essential tool to architecture design and performance evaluation in both scientific and commercial computing areas. Traditional workload characterization techniques include FLOPS rate, cache miss ratios, CPI (cycles per instruction or IPC, instructions per cycle) etc. With the complexity of sophisticated modern superscalar microprocessors, these traditional characterization techniques are not powerful enough to pinpoint the performance bottleneck of an application on a specific microprocessor. They are also incapable of immediately demonstrating the potential performance benefit of any architectural or functional improvement in a new processor design. To solve these problems, many people rely on simulators, which have substantial constraints especially on large-scale scientific computing applications. This paper presents a new technique of characterizing applications at the instruction level using hardware performance counters. It has the advantage of collecting instruction-level characteristics in a few runs virtually without overhead or slowdown. A variety of instruction counts can be utilized to calculate some average abstract workload parameters corresponding to microprocessor pipelines or functional units. Based on the microprocessor architectural constraints and these calculated abstract parameters, the architectural performance bottleneck for a specific application can be estimated. In particular, the analysis results can provide some insight to the problem that only a small percentage of processor peak performance can be achieved even for many very cache-friendly codes. Meanwhile, the bottleneck estimation can provide suggestions about viable architectural/functional improvement for certain workloads. Eventually, these abstract parameters can lead to the creation of an analytical microprocessor pipeline model and memory hierarchy model.

Physical Description

9 p.

Notes

OSTI as DE00760038

Medium: P; Size: 9 pages

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  • Workshop on Workload Characterization, Dallas, TX (US), 11/24/1998--11/27/1998

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  • Report No.: LA-UR-98-4179
  • Grant Number: W-7405-ENG-36
  • Office of Scientific & Technical Information Report Number: 760038
  • Archival Resource Key: ark:/67531/metadc723082

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Office of Scientific & Technical Information Technical Reports

Reports, articles and other documents harvested from the Office of Scientific and Technical Information.

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  • November 24, 1998

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  • Sept. 29, 2015, 5:31 a.m.

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  • April 11, 2017, 7:37 p.m.

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Luo, Y. & Cameron, K.W. Instruction-Level Characterization of Scientific Computing Applications Using Hardware Performance Counters, article, November 24, 1998; New Mexico. (digital.library.unt.edu/ark:/67531/metadc723082/: accessed December 11, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.