Development of a high density pixel multichip module at Fermilab Page: 3 of 5
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power pad interfaces of FPIX1 extend beyond the edge of the
Wire bonding pads
" Deco pling Caps
Circuit adhesive Sensor
Bump bonds +\
Fiber adhesive -'
Figure 6: Sketch of the Pixel Multichip Module "Stack"
The interconnect circuitry (flex circuit) is placed on the
top of this assembly and the FPIX1 pad interface is wire-
bonded to the flex circuit. The circuit then extends to one end
of the module where low profile connectors interface the
module to the data acquisition system. The large number of
signals in this design imposes space constraints and requires
aggressive design rules, such as 35 pm trace width and trace-
to-trace clearance of 35 pm.
This packaging requires a flex circuit with four layers of
copper traces (as sketched in Figure 7). The data, control and
clock signals use the two top layers, power uses the third layer
and ground and sensor high voltage bias use the bottom layer.
The flex circuit has two power traces, one analog and one
digital. These traces are wide enough to guarantee that the
voltage drop from chip to chip is within the FPIX1 5%
tolerance. The decoupling capacitors in the flex circuit are
close to the pixel chips. The trace lengths and vias that
connect the capacitors to the chips are minimized to reduce
the interconnection inductance. A picture of the flex circuit
made by CERN is shown in Figure 8.
D gmtal lines Analoglines
MetWal Layer 1
E E E EKapton Layer 1
U Meta Layer 3
w Groud Layer 2 -gh voltage
MW Layer 4
Layer 3 _Bias Pad (tn
Figure 8: Flex Circuit Picture
To minimize coupling between digital and analog
elements, signals are grouped together into two different sets.
The digital and analog traces are laid out on top of the digital
and analog power supply traces, respectively. Furthermore, a
ground trace runs between the analog set and the digital set of
A. High Voltage Bias
The pixel sensor is biased with up to 1000 VDC through
the flex circuit. The coupling between the digital traces and
the bias trace has to be minimized to improve the sensor noise
performance. To achieve this, the high voltage trace runs in
the fourth metal layer (ground plane, see Figure 7) and bellow
the analog power supply trace. The high voltage electrically
connects to the sensor bias window through Gold epoxy. An
insulator layer in the bottom of the flex circuit isolates the
ground in the fourth metal layer of the flex circuit from the
high voltage of the pixel sensor.
The interface adhesive between the flex circuit and the
pixel sensor has to compensate for mechanical stress due to
the coefficient of thermal expansion mismatches between the
flex circuit and the silicon pixel sensor. Two alternatives are
being pursued. One is the 3M thermally conductive tape .
The other is the silicone-based adhesive used in .
The present pixel module prototypes were assembled using
the 3M tape with a thickness of 0.05mm. Before mounting the
flex circuit onto the sensor, a set of dummies with bump-bond
structures where used to evaluate the assembly process. This
assembly process led to no noticeable change in the resistance
of the bumps. Figure 9 shows a picture of the dummy.
flex Circuit-Silicon Adhesive
- Gold Foxy
T' a r
Figure 9: Dummy Bump Bond Structure
Figure 7: Sketch of Flex Circuit Cross Section
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al., Sergio Zimmermann et. Development of a high density pixel multichip module at Fermilab, article, September 11, 2001; Batavia, Illinois. (digital.library.unt.edu/ark:/67531/metadc720132/m1/3/: accessed September 25, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.