A two-level fanout system for the CDF silicon vertex tracker Page: 3 of 4
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is active, the Fanout A stops reading new data from the
The SuperStrip number (12 bits) inserted in the word
used by the AM system and the list of 12 enable bits as-
sociated to each XFT track are determined using a Look
Up Table. The Look Up Table is implemented as a set
of 6 (512Kx8 bit) static RAMs where 20 bits summariz-
ing the XFT track parameters are used as an address and
the SuperStrip number and the list of enables are stored in
each location. To obtain a 1M x 24 bit Look Up table, the
6 memories are organized as two blocks of 3 units, with bit
20 of the XFT parameters actually used as a chip select to
enable either the first or the second block of RAMs.
The 2 L1T bits are generated by the A board as a pro-
grammable combinatorial function of the 64 Level 1 Trigger
decisions. The logic of the board is implemented on seven
240 pin FLEX10K20 FPGAs from ALTERA. The firmware
is fully reconfigurable on board.
A.1 Error handling and data flow monitoring
There is a number of error conditions that can be de-
tected by SVT while processing data, for example some-
thing can go wrong in the data transfer and the input FiFo
on one board can become full, or some of the data received
in input by one board are outside the valid range. The
system can both set error flags in the VME register of the
single board and propagate error flags in the data stream
setting appropriate error bits on the End Event word .
The Fanout A can detect 4 out of the 8 possible SVT error
conditions: the Parity Error (if the parity of the input XFT
data does not match the Parity bit of the XFT End Event
word), the Lost Synch (if the L2B of the XFT End Event
word does not match the L2B of the L1 Trigger words),
the FiFo Overflow (if one input FiFo gets full) and the In-
valid Data (if the parameters of one XFT track are outside
the valid address range of the Look Up Table). When the
A board detects one of these conditions, it sets the corre-
sponding error flag in the output End Event word. If one
error bit is already asserted in the input EE word, it is
propagated in the output EE word.
The SVT boards have also a system for data flow mon-
itoring. The input and the output data streams from the
boards are continuously copied to circular memories called
Spy Buffers. In the Fanout A board these memories are
128K static RAMs for the XFT data and 64K both for
the L1 Trigger data and for the output Spy Buffer, which
spies data flowing to the P3 connector. These buffers act
as built-in logic state analizers and help system monitor-
ing and diagnostics. As a consequence of error conditions
these buffers can be frozen and read from VME with no
interruption of the normal data flow.
B. Fanout B board
There are two identical Fanout B boards whose identity
is set by an onboard switch. Their function is to receive the
data from the Fanout A board through the P3 backplane
and to distribute the 23 data bits to the proper SVT wedges
according to the list of enable bits. They have also the
o e Q 7 lE
o Q a
Fig. 1. PCB drawing of the Fanout A board. Left side is front panel
side, right side is VME connectors side.
function to set the Parity bit in the End Event words sent
to the 12 outputs. The Parity of each stream is computed
by the A board and is transmitted to the B boards: when
the EE word is sent from A to B, the 12 enable bits have
a special meaning, each of them is the parity bit of the
corresponding output stream. The B boards insert each
PA bit in the EE word sent to the corresponding output
In addition the B boards control the Hold and Data
Strobe bits of each output stream. Data flow out of each
Fanout B board through the 6 connectors on the front
panel. If the Hold signal is received from any output, the
line on the P3 backplane meaning Hold is set active and the
Fanout A stops reading new data. Each Fanout B receives
the clock from the Fanout A board through the P3 back-
plane and its logical functions are implemented on one 240
pin FLEX10K20 FPGA from Altera. For simplicity this
board has no Spy Buffers and no VME interface.
III. OPERATION MODES
The Fanout system has two different operation modes:
running mode and VME mode. In running mode it
processes the data received through the input connectors
and outputs the proper data to each SVT wedge. The VME
mode is used to write the content of the Look Up Table
used to map the XFT tracks into SuperStrips and for test-
ing purposes. In particular in VME mode the content of
any Spy Buffer can be written from the VME interface and
the board can be forced to process these data as if they
were the actual input streams. In this operating mode
data contained in the input FiFos are disregarded. This
can be done for both the input streams simultaneously as
well as for only one. This allows an almost complete test
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al., A. Bardi et. A two-level fanout system for the CDF silicon vertex tracker, article, November 2, 2001; Batavia, Illinois. (https://digital.library.unt.edu/ark:/67531/metadc718395/m1/3/: accessed April 23, 2019), University of North Texas Libraries, Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.