Memory-intensive benchmarks: IRAM vs. cache-based machines

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The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we explore the performance of a set of memory-intensive benchmarks and use them to compare the performance of conventional cache-based microprocessors to a mixed logic and DRAM processor called VIRAM. The benchmarks are based on problem statements, rather than specific implementations, and in each case we explore the fundamental hardware requirements of the problem, as well as alternative algorithms and data structures that can help expose fine-grained parallelism or simplify memory access patterns. The benchmarks are characterized by their memory ... continued below

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Gaeke, Brian G.; Husbands, Parry; Kim, Hyun Jin; Li, Xiaoye S.; Moon, Hyun Jin; Oliker, Leonid et al. September 29, 2001.

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Description

The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we explore the performance of a set of memory-intensive benchmarks and use them to compare the performance of conventional cache-based microprocessors to a mixed logic and DRAM processor called VIRAM. The benchmarks are based on problem statements, rather than specific implementations, and in each case we explore the fundamental hardware requirements of the problem, as well as alternative algorithms and data structures that can help expose fine-grained parallelism or simplify memory access patterns. The benchmarks are characterized by their memory access patterns, their basic structures, and the ratio of computation to memory operation.

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OSTI as DE00788083

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  • International Parallel and Distributed Processing Symposium, Fort Lauderdale, FL (US), 04/15/2002--04/19/2002

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  • Report No.: LBNL--48979
  • Grant Number: AC03-76SF00098
  • Office of Scientific & Technical Information Report Number: 788083
  • Archival Resource Key: ark:/67531/metadc717918

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  • September 29, 2001

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  • Sept. 29, 2015, 5:31 a.m.

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  • April 4, 2016, 3:28 p.m.

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Gaeke, Brian G.; Husbands, Parry; Kim, Hyun Jin; Li, Xiaoye S.; Moon, Hyun Jin; Oliker, Leonid et al. Memory-intensive benchmarks: IRAM vs. cache-based machines, article, September 29, 2001; Berkeley, California. (digital.library.unt.edu/ark:/67531/metadc717918/: accessed August 16, 2017), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.