Optimizing transformations of stencil operations for parallel cache-based architectures

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This paper describes a new technique for optimizing serial and parallel stencil- and stencil-like operations for cache-based architectures. This technique takes advantage of the semantic knowledge implicity in stencil-like computations. The technique is implemented as a source-to-source program transformation; because of its specificity it could not be expected of a conventional compiler. Empirical results demonstrate a uniform factor of two speedup. The experiments clearly show the benefits of this technique to be a consequence, as intended, of the reduction in cache misses. The test codes are based on a 5-point stencil obtained by the discretization of the Poisson equation and ... continued below

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5 p.

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Bassetti, F. & Davis, K. June 28, 1999.

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Description

This paper describes a new technique for optimizing serial and parallel stencil- and stencil-like operations for cache-based architectures. This technique takes advantage of the semantic knowledge implicity in stencil-like computations. The technique is implemented as a source-to-source program transformation; because of its specificity it could not be expected of a conventional compiler. Empirical results demonstrate a uniform factor of two speedup. The experiments clearly show the benefits of this technique to be a consequence, as intended, of the reduction in cache misses. The test codes are based on a 5-point stencil obtained by the discretization of the Poisson equation and applied to a two-dimensional uniform grid using the Jacobi method as an iterative solver. Results are presented for a 1-D tiling for a single processor, and in parallel using 1-D data partition. For the parallel case both blocking and non-blocking communication are tested. The same scheme of experiments has bee n performed for the 2-D tiling case. However, for the parallel case the 2-D partitioning is not discussed here, so the parallel case handled for 2-D is 2-D tiling with 1-D data partitioning.

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5 p.

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OSTI as DE00757004

Medium: P; Size: 5 pages

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  • 1999 International Conference on Parallel and Distributed Processing Techniques and Applications, Monte Carlo Resort, Las Vegas, NV (US), 06/28/1999--07/01/1999

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  • Report No.: LA-UR-99-1119
  • Grant Number: W-7405-ENG-36
  • Office of Scientific & Technical Information Report Number: 757004
  • Archival Resource Key: ark:/67531/metadc702666

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  • June 28, 1999

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  • Sept. 12, 2015, 6:31 a.m.

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  • April 11, 2017, 12:27 p.m.

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Bassetti, F. & Davis, K. Optimizing transformations of stencil operations for parallel cache-based architectures, article, June 28, 1999; New Mexico. (digital.library.unt.edu/ark:/67531/metadc702666/: accessed December 18, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.