How to build VLSI-efficient neural chips

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This paper presents several upper and lower bounds for the number-of-bits required for solving a classification problem, as well as ways in which these bounds can be used to efficiently build neural network chips. The focus will be on complexity aspects pertaining to neural networks: (1) size complexity and depth (size) tradeoffs, and (2) precision of weights and thresholds as well as limited interconnectivity. They show difficult problems-exponential growth in either space (precision and size) and/or time (learning and depth)-when using neural networks for solving general classes of problems (particular cases may enjoy better performances). The bounds for the number-of-bits ... continued below

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13 p.

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Beiu, V. February 1, 1998.

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Description

This paper presents several upper and lower bounds for the number-of-bits required for solving a classification problem, as well as ways in which these bounds can be used to efficiently build neural network chips. The focus will be on complexity aspects pertaining to neural networks: (1) size complexity and depth (size) tradeoffs, and (2) precision of weights and thresholds as well as limited interconnectivity. They show difficult problems-exponential growth in either space (precision and size) and/or time (learning and depth)-when using neural networks for solving general classes of problems (particular cases may enjoy better performances). The bounds for the number-of-bits required for solving a classification problem represent the first step of a general class of constructive algorithms, by showing how the quantization of the input space could be done in O (m{sup 2}n) steps. Here m is the number of examples, while n is the number of dimensions. The second step of the algorithm finds its roots in the implementation of a class of Boolean functions using threshold gates. It is substantiated by mathematical proofs for the size O (mn/{Delta}), and the depth O [log(mn)/log{Delta}] of the resulting network (here {Delta} is the maximum fan in). Using the fan in as a parameter, a full class of solutions can be designed. The third step of the algorithm represents a reduction of the size and an increase of its generalization capabilities. Extensions by using analogue COMPARISONs, allows for real inputs, and increase the generalization capabilities at the expense of longer training times. Finally, several solutions which can lower the size of the resulting neural network are detailed. The interesting aspect is that they are obtained for limited, or even constant, fan-ins. In support of these claims many simulations have been performed and are called upon.

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13 p.

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OSTI as DE98003416

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  • EIS `97: international symposium on engineering of intelligent systems, Tenerife (Spain), 11-13 Feb 1998

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  • Other: DE98003416
  • Report No.: LA-UR--97-4460
  • Report No.: CONF-980216--
  • Grant Number: W-7405-ENG-36
  • Office of Scientific & Technical Information Report Number: 645482
  • Archival Resource Key: ark:/67531/metadc698812

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  • February 1, 1998

Added to The UNT Digital Library

  • Aug. 14, 2015, 8:43 a.m.

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  • May 5, 2016, 7:32 p.m.

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Beiu, V. How to build VLSI-efficient neural chips, article, February 1, 1998; New Mexico. (digital.library.unt.edu/ark:/67531/metadc698812/: accessed October 19, 2017), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.