Development and Validation of a Hierarchical Memory Model Incorporating CPU- and Memory-Operation Overlap

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Distributed shared memory architectures (DSM`s) such as the Origin 2000 are being implemented which extend the concept of single-processor cache hierarchies across an entire physically-distributed multiprocessor machine. The scalability of a DSM machine is inherently tied to memory hierarchy performance, including such issues as latency hiding techniques in the architecture, global cache-coherence protocols, memory consistency models and, of course, the inherent locality of reference in algorithms of interest. In this paper, we characterize application performance with a {open_quotes}memory-centric{close_quotes} view. Using a simple mean value analysis (MVA) strategy and empirical performance data, we infer the contribution of each level in the ... continued below

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21 p.

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Lubeck, Olaf M.; Luo, Yong; Wasserman, Harvey J. & Bassetti, Federico December 31, 1997.

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Distributed shared memory architectures (DSM`s) such as the Origin 2000 are being implemented which extend the concept of single-processor cache hierarchies across an entire physically-distributed multiprocessor machine. The scalability of a DSM machine is inherently tied to memory hierarchy performance, including such issues as latency hiding techniques in the architecture, global cache-coherence protocols, memory consistency models and, of course, the inherent locality of reference in algorithms of interest. In this paper, we characterize application performance with a {open_quotes}memory-centric{close_quotes} view. Using a simple mean value analysis (MVA) strategy and empirical performance data, we infer the contribution of each level in the memory system to the application`s overall cycles per instruction (cpi). We account for the overlap of processor execution with memory accesses - a key parameter which is not directly measurable on the Origin systems. We infer the separate contributions of three major architecture features in the memory subsystem of the Origin 2000: cache size, outstanding loads-under-miss, and memory latency.

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21 p.

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OSTI as DE98000349

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  • 4. international symposium on high-performance computing architecture, Las Vegas, NV (United States), 1-4 Feb 1998

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  • Other: DE98000349
  • Report No.: LA-UR--97-3462
  • Report No.: CONF-980214--
  • Grant Number: W-7405-ENG-36
  • Office of Scientific & Technical Information Report Number: 621718
  • Archival Resource Key: ark:/67531/metadc693606

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  • December 31, 1997

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  • Aug. 14, 2015, 8:43 a.m.

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  • Feb. 29, 2016, 8:50 p.m.

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Lubeck, Olaf M.; Luo, Yong; Wasserman, Harvey J. & Bassetti, Federico. Development and Validation of a Hierarchical Memory Model Incorporating CPU- and Memory-Operation Overlap, article, December 31, 1997; New Mexico. (digital.library.unt.edu/ark:/67531/metadc693606/: accessed April 24, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.