SVT: an online silicon vertex tracker for the CDF upgrade Page: 6 of 6
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A uniform protocol has been designed for data exchange, using unidirectional differential lines
on a flat cable, with pipeline transfer driven by an asynchronous clock from the source and a
FIFO on the receiving end, which is pushed at every clock cycle. A loose handshake is provided
by an "almost full" signal issued by the FIFO and interpreted by the source as an "HOLD".
The 25 lines cable has 21 data lines, a clock, HOLD, End Packet (EP) and End Event (EE)
signals. An EP bit marks the last word of a packet, while EE marks the end of data for the
current event: each module will issue an EE after it has received an EE at all its inputs.
Hits are received via optical fibers terminated by receivers mounted on transition modules.
The data is transmitted through the backplane to the HF modules containing the hit clustering
logic. Three HF's are required to process one wedge of the SVXII. In a HF, strip address and
PH flow through a shift register: as they go, PH in three adjacent strips is used as address for
a lookup table implementing the clustering algorithm (e.g. adjacent strips with low-high-low
configuration) and containing the cluster center coordinate.
The Merger board can merge four independent input streams into a single output stream, and
is standardized for use in all the system where a merging is needed. Merging is performed on
a first come, first served basis, which preserves the packet structure and the event structure.
EE bit is asserted on output after EE is received on all the input streams.
Each AMbank comprises three boards. The first, called the AM sequencer, receives hit co-
ordinates from the HF and maps them to superstrips, using a lookup table, coordinates various
AM operations, and outputs road info to the HB. The AM chips are housed on two twin boards
(AM boards) connected to the sequencer via a custom backplane (see Fig.1). The current AM
implementation  is a .7 pm full custom CMOS chip with 128 patterns (one pattern has 6
layers of 12 bits each), so each AM board houses 128 AMchips in a tree structure connected
in groups of 8 by an intermediate logic (GLUE), realized on large FPGAs, to perform address
decoding, pipelining and syncronization (Fig. 2 right).
Each HB board works on one wedge, receiving and storing hits and tracks in a Hit Memory,
and the current hit count for each superstrip in a Hit Count Memory (Cache-Tag RAM). The
superstrips associated with a given road are stored in a lookup table in the HB. When a road is
received this information is used to address the Hit Count Memory, and the hits corresponding
to that superstrip are output in a road-info packet.
The TF processor farm receives the road-info packets. Although all N processors receive all
data, each one will only process l/Nth of the packets according to a simple algorithm (e.g.
processor i works on the ith,(i + N)th,(i + 2N)th,... roads. All tracks from all the processors
are merged into a single stream and delivered to a L2 processor.
The hardware just described requires eight standard CDF crates as used for the CDF DAQ
upgrade. Six crates house the HFs, AMs, and HBs for the 12 0 sectors of SVXII. A crate
houses the Merger modules needed to combine output from the 12 sectors and from the 12
Track Fitters into one stream. The last crate can house up to 20 TF modules.
1. M.Dell'Orso and L.Ristori, Nucl. Inst. Meth. A278 (1989), 436-440;
2. SVT Technical Design Report internal note CDF/DOC/TRIGGER/PUBLIC/3108;
3. S.R.Amendolia et al. IEEE Trans. Nucl. Sci. 39 n.4 (1992);
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Bardi, A.; Belforte, S. & Berryhill, J. SVT: an online silicon vertex tracker for the CDF upgrade, article, July 1, 1997; Batavia, Illinois. (digital.library.unt.edu/ark:/67531/metadc690535/m1/6/: accessed February 18, 2019), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.