Analysis of Interlayer Shorts in a 0.5 {micro}m CMOS IC Technology

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Description

Sandia is manufacturing CMOS ICs with 0.5 {micro}m LOCOS and shallow trench isolation (STI) technologies and is developing a 0.35 {micro}m SOI technology. A program based on burn-in and life tests is being used to qualify the 0.5 {micro}m technologies for delivery of high reliability ICs to customers for military and space applications. Representative ICs from baseline wafer lots are assembled using a high reliability process with multilayer hermetic, ceramic packages. These ICs are electrically tested before, during, and after burn-in and subsequent 1000 hour dynamic and static life tests. Two types of ICS are being used for this qualification, ... continued below

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9 p.

Creation Information

Cole, E.I.; Henderson, C.L. & Soden, J.M. March 12, 1999.

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This article is part of the collection entitled: Office of Scientific & Technical Information Technical Reports and was provided by UNT Libraries Government Documents Department to Digital Library, a digital repository hosted by the UNT Libraries. More information about this article can be viewed below.

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  • Sandia National Laboratories
    Publisher Info: Sandia National Labs., Albuquerque, NM, and Livermore, CA
    Place of Publication: Albuquerque, New Mexico

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Description

Sandia is manufacturing CMOS ICs with 0.5 {micro}m LOCOS and shallow trench isolation (STI) technologies and is developing a 0.35 {micro}m SOI technology. A program based on burn-in and life tests is being used to qualify the 0.5 {micro}m technologies for delivery of high reliability ICs to customers for military and space applications. Representative ICs from baseline wafer lots are assembled using a high reliability process with multilayer hermetic, ceramic packages. These ICs are electrically tested before, during, and after burn-in and subsequent 1000 hour dynamic and static life tests. Two types of ICS are being used for this qualification, a 256K bit SRAM and a Microcontroller Core (MCC). Over 600 ICs have successfully completed these qualification tests, resulting in a failure rate estimate of less than 4 FITS for satellite applications. Recently, a group of SRAMS from a development wafer lot incorporating nonqualified processes of the 0.5 {micro}m LOCOS technology had an unusually high number of failures during the initial electrical test after packaging. The investigation of these failures is described.

Physical Description

9 p.

Notes

OSTI as DE00004255

Medium: P; Size: 9 pages

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  • Journal Name: Electronic Device Failure Analysis News (EDFAN); Other Information: Submitted to Electronic Device Failure Analysis News (EDFAN)

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  • Report No.: SAND99-0600J
  • Grant Number: AC04-94AL85000
  • Office of Scientific & Technical Information Report Number: 4255
  • Archival Resource Key: ark:/67531/metadc682806

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Office of Scientific & Technical Information Technical Reports

Reports, articles and other documents harvested from the Office of Scientific and Technical Information.

Office of Scientific and Technical Information (OSTI) is the Department of Energy (DOE) office that collects, preserves, and disseminates DOE-sponsored research and development (R&D) results that are the outcomes of R&D projects or other funded activities at DOE labs and facilities nationwide and grantees at universities and other institutions.

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  • March 12, 1999

Added to The UNT Digital Library

  • July 25, 2015, 2:20 a.m.

Description Last Updated

  • April 11, 2017, 7:30 p.m.

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Cole, E.I.; Henderson, C.L. & Soden, J.M. Analysis of Interlayer Shorts in a 0.5 {micro}m CMOS IC Technology, article, March 12, 1999; Albuquerque, New Mexico. (digital.library.unt.edu/ark:/67531/metadc682806/: accessed November 19, 2017), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.