Use of air gap structures to lower intralevel capacitance Page: 1 of 9
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USE OF AIR GAP STRUCTURES TO LOWER INTRALEVEL
J.G.Fleming* and E.Roherty-Osmun
P.O. Box 5800
Sandia National Laboratories 7
Albuquerque NM 87185.
Interconnect delays, arising in part from intralevel capacitance, are one of the factors
limiting the performance of advanced integrated circuits. In addition, the problem of
filling the spaces between neighboring metal lines with an insulator is becoming
increasingly acute as aspect ratios increase. We address these problems simultaneously
by intentionally creating an air gap between closely spaced metal lines. Undesirable
topography is eliminated using a spin-on dielectric. We then cap the wafers with silicon
dioxide and planarize'using chemical mechanical polishing. Simple modeling of test
structures predicts an equivalent dielectric constant of 1.9 on features similar to those
expected for 0.25 micron technologies. Two level metal test structures fabricated in a 0.5
micron CMOS technology show that the process can be readily integrated with current
standard CMOS processes. The potential problems of via misalignment, overall dielectric
stack height, and the relative difficulty of ensuring void formation compared to that of
ensuring a void-free fill are considered.
As device dimensions continue to shrink, system performance is becoming limited by the
interconnect delay. This is a major unresolved challenge to the semiconductor industry. A
major component of this delay arises from intralevel capacitance . A variety of
different techniques have been pursued to address this problem. The use of inorganic
spin-on materials, for example hydrogen silsesquioxane (HSQ), is relatively advanced.
However, HSQ only reduces the dielectric constant to -3.0 . Fluorinated silicon
dioxides can be deposited by chemical vapor deposition (CVD) through the addition of a
fluorine containing species to the reactive gas flow, but film stability appears to limit the
reduction in the dielectric constant to -3.5 . Spin-on organic materials demonstrate
low dielectric constants. However, they suffer from a number of problems such as poor
adhesion, low thermal stability, low thermal conductivity, high thermal expansion
coefficients, low dielectric strengths, and high leakage currents. Via etch integration
problems can also be significant, see for example Ref. 4. Organic dielectrics can be
deposited by CVD, however, the deposition processes are not well developed. Another
proposed approach is the use of porous materials such as Xerogels . Since a large
fraction of these materials is air, they have low dielectric constants. However, it is clear
that these materials also potentially face severe process integration issues.
A second problem being encountered is that the metal thickness is not scaling down as
fast as the metal pitch is shrinking. This results in increasing aspect ratios between metal
lines. This trend has driven interlevel dielectric oxide deposition systems to become
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Fleming, J.G. & Roherty-Osmun, E. Use of air gap structures to lower intralevel capacitance, article, March 1, 1997; Albuquerque, New Mexico. (digital.library.unt.edu/ark:/67531/metadc674146/m1/1/: accessed October 15, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.