Use of air gap structures to lower intralevel capacitance

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Interconnect delays, arising in part from intralevel capacitance, are one of the factors limiting the performance of advanced circuits. In addition, the problem of filling the spaces between neighboring metal lines with an insulator is becoming increasingly acute as aspect ratios increase. We address these problems simultaneously by intentionally creating an air gap between closely spaced metal lines. Undesirable topography is eliminated using a spin-on dielectric. We then cap the wafers with silicon dioxide and planarize using chemical mechanical polishing. Simple modeling of test structures predicts an equivalent dielectric constant of 1.9 on features similar to those expected for 0.25 ... continued below

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8 p.

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Fleming, J.G. & Roherty-Osmun, E. March 1, 1997.

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This article is part of the collection entitled: Office of Scientific & Technical Information Technical Reports and was provided by UNT Libraries Government Documents Department to Digital Library, a digital repository hosted by the UNT Libraries. It has been viewed 68 times . More information about this article can be viewed below.

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  • Sandia National Laboratories
    Publisher Info: Sandia National Labs., Albuquerque, NM (United States)
    Place of Publication: Albuquerque, New Mexico

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Description

Interconnect delays, arising in part from intralevel capacitance, are one of the factors limiting the performance of advanced circuits. In addition, the problem of filling the spaces between neighboring metal lines with an insulator is becoming increasingly acute as aspect ratios increase. We address these problems simultaneously by intentionally creating an air gap between closely spaced metal lines. Undesirable topography is eliminated using a spin-on dielectric. We then cap the wafers with silicon dioxide and planarize using chemical mechanical polishing. Simple modeling of test structures predicts an equivalent dielectric constant of 1.9 on features similar to those expected for 0.25 micron technologies. Two level metal test structures fabricated in a 0.5 micron CMOS technology show that the process can be readily integrated with current standard CMOS processes. The potential problems of via misalignment, overall dielectric stack height, and the relative difficulty of ensuring void formation compared to that of ensuring a void-free fill are considered.

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8 p.

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OSTI as DE97003197

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  • 97 dielectrics for ULSI multilevel interconnection, Santa Clara, CA (United States), 10-11 Feb 1997

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  • Other: DE97003197
  • Report No.: SAND--97-0330C
  • Report No.: CONF-970250--1
  • Grant Number: AC04-94AL85000
  • Office of Scientific & Technical Information Report Number: 442165
  • Archival Resource Key: ark:/67531/metadc674146

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  • March 1, 1997

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  • July 25, 2015, 2:21 a.m.

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  • April 14, 2016, 2:04 p.m.

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Fleming, J.G. & Roherty-Osmun, E. Use of air gap structures to lower intralevel capacitance, article, March 1, 1997; Albuquerque, New Mexico. (digital.library.unt.edu/ark:/67531/metadc674146/: accessed September 24, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.