Use of air gap structures to lower intralevel capacitance

PDF Version Also Available for Download.

Description

Interconnect delays, arising in part from intralevel capacitance, are one of the factors limiting the performance of advanced circuits. In addition, the problem of filling the spaces between neighboring metal lines with an insulator is becoming increasingly acute as aspect ratios increase. We address these problems simultaneously by intentionally creating an air gap between closely spaced metal lines. Undesirable topography is eliminated using a spin-on dielectric. We then cap the wafers with silicon dioxide and planarize using chemical mechanical polishing. Simple modeling of test structures predicts an equivalent dielectric constant of 1.9 on features similar to those expected for 0.25 … continued below

Physical Description

8 p.

Creation Information

Fleming, J.G. & Roherty-Osmun, E. March 1, 1997.

Context

This article is part of the collection entitled: Office of Scientific & Technical Information Technical Reports and was provided by the UNT Libraries Government Documents Department to the UNT Digital Library, a digital repository hosted by the UNT Libraries. It has been viewed 155 times. More information about this article can be viewed below.

Who

People and organizations associated with either the creation of this article or its content.

Sponsor

Publisher

  • Sandia National Laboratories
    Publisher Info: Sandia National Labs., Albuquerque, NM (United States)
    Place of Publication: Albuquerque, New Mexico

Provided By

UNT Libraries Government Documents Department

Serving as both a federal and a state depository library, the UNT Libraries Government Documents Department maintains millions of items in a variety of formats. The department is a member of the FDLP Content Partnerships Program and an Affiliated Archive of the National Archives.

Contact Us

What

Descriptive information to help identify this article. Follow the links below to find similar items on the Digital Library.

Description

Interconnect delays, arising in part from intralevel capacitance, are one of the factors limiting the performance of advanced circuits. In addition, the problem of filling the spaces between neighboring metal lines with an insulator is becoming increasingly acute as aspect ratios increase. We address these problems simultaneously by intentionally creating an air gap between closely spaced metal lines. Undesirable topography is eliminated using a spin-on dielectric. We then cap the wafers with silicon dioxide and planarize using chemical mechanical polishing. Simple modeling of test structures predicts an equivalent dielectric constant of 1.9 on features similar to those expected for 0.25 micron technologies. Two level metal test structures fabricated in a 0.5 micron CMOS technology show that the process can be readily integrated with current standard CMOS processes. The potential problems of via misalignment, overall dielectric stack height, and the relative difficulty of ensuring void formation compared to that of ensuring a void-free fill are considered.

Physical Description

8 p.

Notes

OSTI as DE97003197

Source

  • 97 dielectrics for ULSI multilevel interconnection, Santa Clara, CA (United States), 10-11 Feb 1997

Language

Item Type

Identifier

Unique identifying numbers for this article in the Digital Library or other systems.

  • Other: DE97003197
  • Report No.: SAND--97-0330C
  • Report No.: CONF-970250--1
  • Grant Number: AC04-94AL85000
  • Office of Scientific & Technical Information Report Number: 442165
  • Archival Resource Key: ark:/67531/metadc674146

Collections

This article is part of the following collection of related materials.

Office of Scientific & Technical Information Technical Reports

Reports, articles and other documents harvested from the Office of Scientific and Technical Information.

Office of Scientific and Technical Information (OSTI) is the Department of Energy (DOE) office that collects, preserves, and disseminates DOE-sponsored research and development (R&D) results that are the outcomes of R&D projects or other funded activities at DOE labs and facilities nationwide and grantees at universities and other institutions.

What responsibilities do I have when using this article?

When

Dates and time periods associated with this article.

Creation Date

  • March 1, 1997

Added to The UNT Digital Library

  • July 25, 2015, 2:21 a.m.

Description Last Updated

  • April 14, 2016, 2:04 p.m.

Usage Statistics

When was this article last used?

Yesterday: 0
Past 30 days: 2
Total Uses: 155

Interact With This Article

Here are some suggestions for what to do next.

Start Reading

PDF Version Also Available for Download.

International Image Interoperability Framework

IIF Logo

We support the IIIF Presentation API

Fleming, J.G. & Roherty-Osmun, E. Use of air gap structures to lower intralevel capacitance, article, March 1, 1997; Albuquerque, New Mexico. (https://digital.library.unt.edu/ark:/67531/metadc674146/: accessed April 19, 2024), University of North Texas Libraries, UNT Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.

Back to Top of Screen