The single-chip FASTBUS Slave Interface

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A single-chip implementation of the general-purpose FASTBUS Slave Interface (FSI) has been developed in ECL gate-array technology. The FSI will occupy only 1.6% of the available circuit board space while providing a complete 32-bit interface to the FASTBUS. All mandatory slave-interface requirements of IEEE 960 are supported, in addition to several non-mandatory requirements and the optional, extended MS code features. Geographic, logical, and broadcast addressing are implemented using on-chip registers. An optional multiple-module addressing technique is included that allows participating modules residing on a common crate or cable segment to respond as if individually addressed in sequence. The user interface ... continued below

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5 p.

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Nelson, R.O.; Machen, D.R. & Downing, R.W. December 31, 1990.

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Description

A single-chip implementation of the general-purpose FASTBUS Slave Interface (FSI) has been developed in ECL gate-array technology. The FSI will occupy only 1.6% of the available circuit board space while providing a complete 32-bit interface to the FASTBUS. All mandatory slave-interface requirements of IEEE 960 are supported, in addition to several non-mandatory requirements and the optional, extended MS code features. Geographic, logical, and broadcast addressing are implemented using on-chip registers. An optional multiple-module addressing technique is included that allows participating modules residing on a common crate or cable segment to respond as if individually addressed in sequence. The user interface provided by the FSI allows control of slave status-response and connection timing for both address and data cycles. The BIT1 ECL array technology used for the FSI allows direct connections to the FASTBUS, eliminating the need for external driver/receiver buffers.

Physical Description

5 p.

Notes

OSTI as DE96006643

Source

  • Institute for Electrical and Electronics Engineers (IEEE) nuclear science symposium, San Francisco, CA (United States), 15-19 Jan 1990

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  • Other: DE96006643
  • Report No.: CONF-900143--40
  • Grant Number: AC02-87ER80454
  • Office of Scientific & Technical Information Report Number: 205218
  • Archival Resource Key: ark:/67531/metadc670624

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Office of Scientific & Technical Information Technical Reports

Reports, articles and other documents harvested from the Office of Scientific and Technical Information.

Office of Scientific and Technical Information (OSTI) is the Department of Energy (DOE) office that collects, preserves, and disseminates DOE-sponsored research and development (R&D) results that are the outcomes of R&D projects or other funded activities at DOE labs and facilities nationwide and grantees at universities and other institutions.

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  • December 31, 1990

Added to The UNT Digital Library

  • June 29, 2015, 9:42 p.m.

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  • Dec. 3, 2015, 8:28 p.m.

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Nelson, R.O.; Machen, D.R. & Downing, R.W. The single-chip FASTBUS Slave Interface, article, December 31, 1990; United States. (digital.library.unt.edu/ark:/67531/metadc670624/: accessed October 24, 2017), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.