Integrated readout electronics for the PbWO{sub 4} photon spectrometer Page: 3 of 5
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probable that off-line sewing corrections can be eliminated
by the use of a CFD.
DC Feedback
D e l a y r
FFract iu CD o
Coin.
Gate
.Arm
Thresh.
Figure 5. CFD Topology-.
Figure 6. CFD Walk Vs. Amplitude for 4 Channels of
CMOS CFD Prototype.
The time-to-amplitude converter (TAC) will
measure the time interval between the discriminator output
and the subsequent beam clock. As shown in figure 7, the
TAC proposed here is of the gated charge integrator type.
Initially the capacitor is held reset by the feedback switch
and the current is flowing into the virtual node of the
amplifier. When a start signal arrives, the feedback switch
is opened and the current source starts to charge the
capacitor. When the stop signal arrives, the current source
is switched away from the virtual node of the amplifier and
the capacitor voltage holds at that value. A reset is
accomplished by putting the switches back in the initial
state. A similar TAC was developed for use in the WA-98
Pb-glass calorimeter. The performance of this TAC is
given in table 2.%tart
79,
tstnp- TAC Out
Figure 7. TAC Block Diagram
Table 2. TAC PerformanceConversion Range (Full-
Scale) Settable from 20 ns to 1 ps
Power Consumption = 1 mW
INL 0.1% from 5 ns to FS
Settling Time <100 ns
Reset Time <50 ns2.3 Analog-to-Digital Conversion (ADC)
Figure 8 is a block diagram of the l-bit ADC
proposed for the FEC. A prototype of this circuit has been
fabricated and tested. The prototype ADC is an 11-bit
Wilkinson type with a maximum dynamic range of 4.5
Volts. The Gray code counter uses a positive ECL logic
level, differential clock input with frequencies as high as
200 MHz. Since the Gray-code counter is double-edge
triggered, the maximum counting rate is 400 MHz.
The ramp generation circuit consists of a an
operational amplifier with an on-chip feedback capacitor to
form an integrator. The ramp and comparator circuits use a
separate analog power and ground connection from the rest
of the digital sections of the chip allowing better
performance from the ADC. The ADC chip consumes = 5
mW per channel. At a clock rate of 100 MHz, an l-bit
conversion requires 10.2 ps. Some key performance
parameters are shown in table 3.
We propose one ADC channel for each THA and
TAC output so that conversions can be performed in
parallel to reduce the deadtime. The ADC clock will be
disabled except during the conversion to prevent clock-
edge coupling into the energy or timing channels during
signal acquisition.
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Simpson, M. L.; Alley, G. T. & Awes, T. Integrated readout electronics for the PbWO{sub 4} photon spectrometer, article, December 31, 1995; Tennessee. (https://digital.library.unt.edu/ark:/67531/metadc664832/m1/3/: accessed April 25, 2024), University of North Texas Libraries, UNT Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.