A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip

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Many high energy physics and nuclear science applications require sub-nanosecond time resolution measurements over many thousands of detector channels. Phase-locked loops have been employed in the past to obtain accurate time references for these measurements. An alternative solution, based on a delay-locked loop (DLL) is described. This solution allows for a very high level of integration yet still offers resolution in the sub-nanosecond regime. Two variations on this solution are outlined. A novel phase detector, based on the Muller C element, is used to implement a charge pump where the injected charge approaches zero as the loop approaches lock on ... continued below

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3 p.

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Santos, D.M.; Dow, S.F. & Levi, M.E. December 1, 1995.

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Description

Many high energy physics and nuclear science applications require sub-nanosecond time resolution measurements over many thousands of detector channels. Phase-locked loops have been employed in the past to obtain accurate time references for these measurements. An alternative solution, based on a delay-locked loop (DLL) is described. This solution allows for a very high level of integration yet still offers resolution in the sub-nanosecond regime. Two variations on this solution are outlined. A novel phase detector, based on the Muller C element, is used to implement a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge of an input clock reference. This greatly reduces timing jitter. In the second variation the loop locks to both the leading and trailing clock edges. In this second implementation, software coded layout generators are used to automatically layout a highly integrated, multi-channel, time to digital converter (TDC). Complex clock generation can be, achieved by taking symmetric taps off the delay elements. The two circuits, DLL and TDC, were implemented in a CMOS 1.2{mu}m and 0.8{mu}m technology, respectively. Test results show a timing jitter of less than 35 ps for the DLL circuit and better solution for the TDC circuit.

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3 p.

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INIS; OSTI as DE96004713

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  • IEEE nuclear science symposium and medical imaging conference, San Francisco, CA (United States), 21-28 Oct 1995

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  • Other: DE96004713
  • Report No.: LBL--38040
  • Report No.: CONF-951073--14
  • Grant Number: AC03-76SF00098
  • Office of Scientific & Technical Information Report Number: 197825
  • Archival Resource Key: ark:/67531/metadc664250

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Office of Scientific & Technical Information Technical Reports

Reports, articles and other documents harvested from the Office of Scientific and Technical Information.

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  • December 1, 1995

Added to The UNT Digital Library

  • June 29, 2015, 9:42 p.m.

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  • April 5, 2016, 11:31 a.m.

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Santos, D.M.; Dow, S.F. & Levi, M.E. A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip, article, December 1, 1995; California. (digital.library.unt.edu/ark:/67531/metadc664250/: accessed November 14, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.