Fast and slow border traps in MOS devices

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In this paper we apply a ``dual-transistor border-trap`` (DTBT) technique that combines high-frequency charge-pumping and lower-frequency threshold-voltage measurements to estimate bulk-oxide-trap, interface-trap, and border-trap densities in irradiated MOS transistors. This method takes advantage of the different time scales in which interface traps and border traps exchange charge with the Si to obtain an estimate of the density of faster border traps often mistaken for interface traps. Effects of slower border traps are also inferred from changes in the ``bulk`` oxide-trap charge density through switched-bias annealing. To our knowledge, this is the first time fast and slow border-trap effects have been ... continued below

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3 p.

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Fleetwood, D.M.; Warren, W.L.; Schwank, J.R.; Winokur, P.S.; Shaneyfelt, M.R. & Riewe, L.C. September 1, 1995.

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  • Sandia National Laboratories
    Publisher Info: Sandia National Labs., Albuquerque, NM (United States)
    Place of Publication: Albuquerque, New Mexico

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Description

In this paper we apply a ``dual-transistor border-trap`` (DTBT) technique that combines high-frequency charge-pumping and lower-frequency threshold-voltage measurements to estimate bulk-oxide-trap, interface-trap, and border-trap densities in irradiated MOS transistors. This method takes advantage of the different time scales in which interface traps and border traps exchange charge with the Si to obtain an estimate of the density of faster border traps often mistaken for interface traps. Effects of slower border traps are also inferred from changes in the ``bulk`` oxide-trap charge density through switched-bias annealing. To our knowledge, this is the first time fast and slow border-trap effects have been separated quantitatively in MOS devices. Possible microstructures for fast and slow border traps are suggested.

Physical Description

3 p.

Notes

OSTI as DE95017550

Source

  • IEEE semiconductor interface specialists conference, Charleston, SC (United States), 7-9 Dec 1995

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  • Other: DE95017550
  • Report No.: SAND--95-1935C
  • Report No.: CONF-951247--1
  • Grant Number: AC04-94AL85000
  • Office of Scientific & Technical Information Report Number: 115649
  • Archival Resource Key: ark:/67531/metadc622370

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Office of Scientific & Technical Information Technical Reports

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  • September 1, 1995

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  • June 16, 2015, 7:43 a.m.

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  • June 23, 2016, 3:49 p.m.

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Fleetwood, D.M.; Warren, W.L.; Schwank, J.R.; Winokur, P.S.; Shaneyfelt, M.R. & Riewe, L.C. Fast and slow border traps in MOS devices, article, September 1, 1995; Albuquerque, New Mexico. (digital.library.unt.edu/ark:/67531/metadc622370/: accessed April 27, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.