Stress Voiding in IC Interconnects - Rules of Evidence for Failure Analysts

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Description

Mention the words ''stress voiding'', and everyone from technology engineer to manager to customer is likely to cringe. This IC failure mechanism elicits fear because it is insidious, capricious, and difficult to identify and arrest. There are reasons to believe that a damascene-copper future might be void-free. Nevertheless, engineers who continue to produce ICs with Al-alloy interconnects, or who assess the reliability of legacy ICs with long service life, need up-to-date insights and techniques to deal with stress voiding problems. Stress voiding need not be fearful. Not always predictable, neither is it inevitable. On the contrary, stress voids are caused ... continued below

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9 p.

Creation Information

FILTER, WILLIAM F. September 17, 1999.

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This article is part of the collection entitled: Office of Scientific & Technical Information Technical Reports and was provided by UNT Libraries Government Documents Department to Digital Library, a digital repository hosted by the UNT Libraries. More information about this article can be viewed below.

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  • Sandia National Laboratories
    Publisher Info: Sandia National Labs., Albuquerque, NM, and Livermore, CA (United States)
    Place of Publication: Albuquerque, New Mexico

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Description

Mention the words ''stress voiding'', and everyone from technology engineer to manager to customer is likely to cringe. This IC failure mechanism elicits fear because it is insidious, capricious, and difficult to identify and arrest. There are reasons to believe that a damascene-copper future might be void-free. Nevertheless, engineers who continue to produce ICs with Al-alloy interconnects, or who assess the reliability of legacy ICs with long service life, need up-to-date insights and techniques to deal with stress voiding problems. Stress voiding need not be fearful. Not always predictable, neither is it inevitable. On the contrary, stress voids are caused by specific, avoidable processing errors. Analytical work, though often painful, can identify these errors when stress voiding occurs, and vigilance in monitoring the improved process can keep it from recurring. In this article, they show that a methodical, forensics approach to failure analysis can solve suspected cases of stress voiding. This approach uses new techniques, and patiently applies familiar ones, to develop evidence meeting strict standards of proof.

Physical Description

9 p.

Notes

OSTI as DE00012671

Medium: P; Size: 9 pages

Source

  • Journal Name: Electronic Device Failure Analysis News; Other Information: Submitted to Electronic Device Failure Analysis News

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  • Report No.: SAND99-2361J
  • Grant Number: AC04-94AL85000
  • Office of Scientific & Technical Information Report Number: 12671
  • Archival Resource Key: ark:/67531/metadc620737

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Office of Scientific & Technical Information Technical Reports

Reports, articles and other documents harvested from the Office of Scientific and Technical Information.

Office of Scientific and Technical Information (OSTI) is the Department of Energy (DOE) office that collects, preserves, and disseminates DOE-sponsored research and development (R&D) results that are the outcomes of R&D projects or other funded activities at DOE labs and facilities nationwide and grantees at universities and other institutions.

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  • September 17, 1999

Added to The UNT Digital Library

  • June 16, 2015, 7:43 a.m.

Description Last Updated

  • April 11, 2017, 9:06 p.m.

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FILTER, WILLIAM F. Stress Voiding in IC Interconnects - Rules of Evidence for Failure Analysts, article, September 17, 1999; Albuquerque, New Mexico. (digital.library.unt.edu/ark:/67531/metadc620737/: accessed October 20, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.