Design and Optimization of Components in a 45nm CMOS Phase Locked Loop

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Description

A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a systematic optimization of each ... continued below

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Sarivisetti, Gayathri December 2006.

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  • Sarivisetti, Gayathri

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Description

A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a systematic optimization of each of its components, and an analog and mixed signal behavioral design approach have been implemented using cadence custom IC design tools.

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UNT Theses and Dissertations

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  • December 2006

Added to The UNT Digital Library

  • May 5, 2008, 3:10 p.m.

Description Last Updated

  • Jan. 15, 2014, 2:47 p.m.

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Citations, Rights, Re-Use

Sarivisetti, Gayathri. Design and Optimization of Components in a 45nm CMOS Phase Locked Loop, thesis, December 2006; Denton, Texas. (digital.library.unt.edu/ark:/67531/metadc5397/: accessed November 19, 2017), University of North Texas Libraries, Digital Library, digital.library.unt.edu; .