VLSI Architecture and FPGA Prototyping of a Secure Digital Camera for Biometric Application

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Description

This thesis presents a secure digital camera (SDC) that inserts biometric data into images found in forms of identification such as the newly proposed electronic passport. However, putting biometric data in passports makes the data vulnerable for theft, causing privacy related issues. An effective solution to combating unauthorized access such as skimming (obtaining data from the passport's owner who did not willingly submit the data) or eavesdropping (intercepting information as it moves from the chip to the reader) could be judicious use of watermarking and encryption at the source end of the biometric process in hardware like digital camera or ... continued below

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Adamo, Oluwayomi Bamidele August 2006.

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  • Adamo, Oluwayomi Bamidele.

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Description

This thesis presents a secure digital camera (SDC) that inserts biometric data into images found in forms of identification such as the newly proposed electronic passport. However, putting biometric data in passports makes the data vulnerable for theft, causing privacy related issues. An effective solution to combating unauthorized access such as skimming (obtaining data from the passport's owner who did not willingly submit the data) or eavesdropping (intercepting information as it moves from the chip to the reader) could be judicious use of watermarking and encryption at the source end of the biometric process in hardware like digital camera or scanners etc. To address such issues, a novel approach and its architecture in the framework of a digital camera, conceptualized as an SDC is presented. The SDC inserts biometric data into passport image with the aid of watermarking and encryption processes. The VLSI (very large scale integration) architecture of the functional units of the SDC such as watermarking and encryption unit is presented. The result of the hardware implementation of Rijndael advanced encryption standard (AES) and a discrete cosine transform (DCT) based visible and invisible watermarking algorithm is presented. The prototype chip can carry out simultaneous encryption and watermarking, which to our knowledge is the first of its kind. The encryption unit has a throughput of 500 Mbit/s and the visible and invisible watermarking unit has a max frequency of 96.31 MHz and 256 MHz respectively.

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  • August 2006

Added to The UNT Digital Library

  • May 5, 2008, 2:43 p.m.

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  • Jan. 15, 2014, 1:50 p.m.

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Citations, Rights, Re-Use

Adamo, Oluwayomi Bamidele. VLSI Architecture and FPGA Prototyping of a Secure Digital Camera for Biometric Application, thesis, August 2006; Denton, Texas. (digital.library.unt.edu/ark:/67531/metadc5393/: accessed June 24, 2017), University of North Texas Libraries, Digital Library, digital.library.unt.edu; .