Split array and scalar data cache: A comprehensive study of data cache organization. Metadata

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Title

  • Main Title Split array and scalar data cache: A comprehensive study of data cache organization.

Creator

  • Author: Naz, Afrin
    Creator Type: Personal

Contributor

  • Chair: Kavi, Krishna M.
    Contributor Type: Personal
    Contributor Info: Major Professor
  • Committee Member: Sweany, Philip H.
    Contributor Type: Personal
    Contributor Info: Minor Professor
  • Committee Member: Brazile, Robert
    Contributor Type: Personal
  • Committee Member: Tate, Stephen R.
    Contributor Type: Personal

Publisher

  • Name: University of North Texas
    Place of Publication: Denton, Texas

Date

  • Creation: 2007-08
  • Digitized: 2007-10-29

Language

  • English

Description

  • Content Description: Existing cache organization suffers from the inability to distinguish different types of localities, and non-selectively cache all data rather than making any attempt to take special advantage of the locality type. This causes unnecessary movement of data among the levels of the memory hierarchy and increases in miss ratio. In this dissertation I propose a split data cache architecture that will group memory accesses as scalar or array references according to their inherent locality and will subsequently map each group to a dedicated cache partition. In this system, because scalar and array references will no longer negatively affect each other, cache-interference is diminished, delivering better performance. Further improvement is achieved by the introduction of victim cache, prefetching, data flattening and reconfigurability to tune the array and scalar caches for specific application. The most significant contribution of my work is the introduction of novel cache architecture for embedded microprocessor platforms. My proposed cache architecture uses reconfigurability coupled with split data caches to reduce area and power consumed by cache memories while retaining performance gains. My results show excellent reductions in both memory size and memory access times, translating into reduced power consumption. Since there was a huge reduction in miss rates at L-1 caches, further power reduction is achieved by partially or completely shutting down L-2 data or L-2 instruction caches. The saving in cache sizes resulting from these designs can be used for other processor activities including instruction and data prefetching, branch-prediction buffers. The potential benefits of such techniques for embedded applications have been evaluated in my work. I also explore how my cache organization performs for non-numeric data structures. I propose a novel idea called "Data flattening" which is a profile based memory allocation technique to compress sparsely scattered pointer data into regular contiguous memory locations and explore the potentials of my proposed Spit cache organization for data treated with data flattening method.

Subject

  • Keyword: Split data cache
  • Keyword: reconfigurability
  • Keyword: data flattening
  • Keyword: locality of reference
  • Library of Congress Subject Headings: Cache memory.
  • Library of Congress Subject Headings: File organization (Computer science)

Collection

  • Name: UNT Theses and Dissertations
    Code: UNTETD

Institution

  • Name: UNT Libraries
    Code: UNT

Rights

  • Rights Access: public
  • Rights License: copyright
  • Rights Holder: Naz, Afrin
  • Rights Statement: Copyright is held by the author, unless otherwise noted. All rights reserved.

Resource Type

  • Thesis or Dissertation

Format

  • Text

Identifier

  • OCLC: 192002228
  • Archival Resource Key: ark:/67531/metadc3932

Degree

  • Degree Name: Doctor of Philosophy
  • Degree Level: Doctoral
  • Degree Discipline: Computer Science
  • Academic Department: Department of Computer Science and Engineering
  • Degree Grantor: University of North Texas

Note