A New N-way Reconfigurable Data Cache Architecture for Embedded Systems

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Performance and power consumption are most important issues while designing embedded systems. Several studies have shown that cache memory consumes about 50% of the total power in these systems. Thus, the architecture of the cache governs both performance and power usage of embedded systems. A new N-way reconfigurable data cache is proposed especially for embedded systems. This thesis explores the issues and design considerations involved in designing a reconfigurable cache. The proposed reconfigurable data cache architecture can be configured as direct-mapped, two-way, or four-way set associative using a mode selector. The module has been designed and simulated in Xilinx ISE ... continued below

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Bani, Ruchi Rastogi December 2009.

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  • Bani, Ruchi Rastogi

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Performance and power consumption are most important issues while designing embedded systems. Several studies have shown that cache memory consumes about 50% of the total power in these systems. Thus, the architecture of the cache governs both performance and power usage of embedded systems. A new N-way reconfigurable data cache is proposed especially for embedded systems. This thesis explores the issues and design considerations involved in designing a reconfigurable cache. The proposed reconfigurable data cache architecture can be configured as direct-mapped, two-way, or four-way set associative using a mode selector. The module has been designed and simulated in Xilinx ISE 9.1i and ModelSim SE 6.3e using the Verilog hardware description language.

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  • December 2009

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  • March 17, 2010, 11:40 a.m.

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  • April 5, 2010, 11:47 a.m.

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Bani, Ruchi Rastogi. A New N-way Reconfigurable Data Cache Architecture for Embedded Systems, thesis, December 2009; Denton, Texas. (digital.library.unt.edu/ark:/67531/metadc12079/: accessed April 30, 2017), University of North Texas Libraries, Digital Library, digital.library.unt.edu; .