Multi-processor developments in the United States for future high energy physics experiments and accelerators Page: 4 of 10
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the name of FUSE, for FASTBUS Uniform System Elements. The proposal is aimed at
architectures for greatly increased data acquisition throughput for next generation fixed
target and collider experiments. The proposal specifies a number of building block functional
units, which can then be combined in a variety of ways to build FASTBUS modules optimized
for different applications.
Presently identified system elements include:
1) FASTBUS Master Interface, which provides a high-speed FASTBUS crate interface
allowing efficient execution of sequential sets of FASTBUS operations for flexible
readout of data from multiple slaves;
2) FASTBUS Auxiliary Port Interface, which provides a second data port onto the
module through the FASTBUS auxiliary connector to any of a number of buses,
including Lecroy ECLine, RS485, SCSI, and ACP Branchbus.
3) Module Control Element, which provides centralized control of the entire module,
including connection to a serial port and a local area network; and
4) Event Processing Units, which provide application specific processing for data
formatting and compression and event monitoring tasks as part of the readout
A typical FASTBUS module will include several processing elements, which can be
digital signal processors, floating point engines, or general purpose processors depending on
the application. These uniform system elements can then be combined into readout controllers,
event builders, and front-end processors for future high-performance data acquisition systems.
3. SECOND GENERATION ACP SYSTEMS - NEW CPUS
Future multiprocessor systems will clearly benefit from the increasingly powerful
processors now becoming available. Besides the "trivial" speedups by using newer versions of
the processors already in use (for example, 25 MHz 68030s replacing 16 MHz 68020s) there are
entirely new families of chips that can be used. In particular, the popular Reduced Instruction
Set Computer (RISC) architecture has led to several new processors. Also heartening is the
trend that the new processors often have software (including FORTRAN and COMPILERS and
UNIX operating systems) available for them even before the hardware is available.
New processors that will offer at least a factor of three, and in some cases a factor of
ten, more performance than the first generation ACP processors include:
1) The R2000 RISC chip from MIPS
2) The Fairchild, now Intergraph Clipper chip set
3) The AM29000 RISC chip from AMD
4) The SPARC RISC chip from SUN
5) The T800 transputer from INMOS
6) The 88000 RISC chip from Motorola
7) The 32532 processor from National Semiconductor
Extravagant claims are made for all of these processors by their manufacturers,
suggesting potential performance of up to 17 million instructions per second (MIPS). Such
claims need to be taken with a grain of salt, as a single instruction does not do the same thing
on different processors. For high energy physics use, a natural standard is to take the VAX
11/780 as representing 1 MIPS in performance, and to measure the new processors only in
comparison to a VAX on high energy physics codes written in high level languages, thus
evaluating both the hardware and the compilers. It matters not how many instructions per
second the CPU can execute if the instructions are not useful in FORTRAN or C and if the
compilers fail to provide sufficient optimization.
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Gaines, I. Multi-processor developments in the United States for future high energy physics experiments and accelerators, article, March 1, 1988; United States. (digital.library.unt.edu/ark:/67531/metadc1204307/m1/4/: accessed January 20, 2019), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.