Solid state high power amplifier for driving the SLC injector klystron Page: 2 of 3
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done it MSC over the put five ye am suggest a mean-time-
tofailure (MTTF) of well over ten years.1 These testa are not
Pulsed operation never lets the temperature of the tran-
sistor junctions stabilise, The collector region carries the bulk
of the current and sees the greatest effect of this tempera-
ture rise. It is believed that the collector N~-layer resistivity
changes due to the temperature change.4 This varying series
resistance together with the collector-base capacitance forms
an RC network which results in an exponential phase change
of approximately 6® during a 5 ps pulse. Increasing input drive
or collector voltage in turn increases the rate or thermal rise
and can be correlated to an increase in phase change during
Collector base capacitance varies with collector voltage.
The phase dependence to collector voltage is approximately
1,5® per volt, Therefore, voltage droop must be kept to a min-
imum or it will compound the problem of phase change during
the pulse. This is done by providing enough energy storage
capacitore necessary tor flat pulse top. We have found 15 pfd
locally for each transistor is sufficient. A printed low-pass fil-
ter on the circuit board isolates the RF from the power supply.
By provid:tg just enough capacitance protects the transistors
from continuous wave (cw) drive or wide pulse width*. The
current limiting series voltage regulator for each module start
limiting at 60 ps pulse length. This is 60% of the recommended
maximum of 100 /is. The emitter base junction can withstand
cw drive. The second protection mechanism is the PIN diode
modulator. It turns the RF drive off in its default position
with no video input.
The 120 W module major components are two 60 W tran-
sistors and two 3 dB 90® branch-line couplers. Matching cir-
cuits and couplers are nucrostrip circuits printed on teflon
fiberglass. The couplers split the input and combine the out-
put power. The isolated ports oi the couplers are terminated
externally to the module. This permits monitoring of circuit
performance during tune-up.
During tune-up, input reflections and power emitted from
isolated ports are minimized while output power is maximized.
Tuning is accomplished by incorporating variable capacitors
on the input and output circuit of each transistor. Initially
collector voltage and input power are set to one-half the final
This minimises transistor damage due to circuit defects and
mistuning. Fine tuning is repeated . 35 V. Final tuning and
voltage setting is based upon power output, pulse shape, mini-
mal phase change during the pulse (Fig, 3), and relative phase
length of the module not to exceed ±10* relativ to a standard
module. Find collector voltage varies between modules from
40 V to 44 V. It has been found that the relative ''base length
between modules eau be kept to within 5® with 'le effort in
tuning. The serial number and voltage is reco: ■ J for each
module. Each module baa its own voltage regulal with cur-
rent limiting. When ^ M together as a system, each module's
VCC supply is adjusted to the recorded value. No tuning is
required for the assembled system.
The four-way splitter/combiner consists of three 3 dB branch-
line couplers. The arrangement of input and output ports is
such that It can be used for splitting and combining power.
Termination of isolated porta is done externally to the atripline
circuit where terminations for the proper power level can be
selected. The stripline circuit itself can handle up to 4 kW of
pulse power without noticeable breakdown.
The interconnecting cables between the splitter/combiner
and 120 W modules are kept to within ±5* relative phase
length. This is accomplished by cutting cable th.- same length
and bending to fit its position. Each cable is then tested on
a network analyser. This simple method produces cables to
within 3d of one another.
Assuming a worst case path length error in the combining
of modules of ±15®, the power output loss would be 0.3 dB
(3.4%). The combining loss noted in the three amplifiers built
is 0.25 to 0.3 dB. This loss is accounted for by conductor loss
in the combiners and cables.
The second stage 32 W amplifier is a product of the same
pulsed transistor technology. It uses a 6 W and 35 W transistor
in series, each with 6 dB gain. These lower power versions of
the 60 W transistor exhibit the same phase change during the
pulse, but to a lesser degree. The phase change for the module
with two transistors in series is approximately 6®.
The 32 dB gain FET amplifier has exhibited no phases
change during the pulse. It is not known whether high-power
pulsed MESFET transistor would, but in this case the FET
amplifier is Class A. Being Class A means it always has bias
current flowing providing DC heating.
The total phase change during the 5 pulse is ) 8® for the
entire system (Fig. 3d). Compensating for the phase change
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Judkins, J.G.; Clendenin, J.E. & Schwarz, H.D. Solid state high power amplifier for driving the SLC injector klystron, article, March 1, 1985; California. (digital.library.unt.edu/ark:/67531/metadc1093760/m1/2/: accessed December 12, 2018), University of North Texas Libraries, Digital Library, digital.library.unt.edu; crediting UNT Libraries Government Documents Department.