Discharge circuits and loads Page: 22 of 62
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DISCHARGE CIRCUITS AND LOADS
FIGURE 7: PULSE TRAN$FORMER LIMITATIONS
Main problem areas are:
1. tR = L : Risetime limit
2. Flatness - determined primarily by resonances in LLCD
and flujx "saturation" level and time, and energy in LE.
3. zF w (L' " LL) CD Falltime limit - especially
if RL is biased diode load.
since LE > L in general
4. Reversal depends upon matching and Q of circuit.
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Sarjeant, W.J. Discharge circuits and loads, report, October 15, 1980; New Mexico. (https://digital.library.unt.edu/ark:/67531/metadc1061299/m1/22/: accessed April 21, 2019), University of North Texas Libraries, Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.