PROGRAMMER'S GUIDE TO THE MICROPROGRAMMED BRANCH DRIVER FOR THE PDP-11. Page: 5 of 16
This report is part of the collection entitled: Office of Scientific & Technical Information Technical Reports and was provided to Digital Library by the UNT Libraries Government Documents Department.
The following text was automatically extracted from the image on this page using optical character recognition software:
GLR: Low-order bits (1-16) of the Graded Lam
(GL) requests; computer CPU program interrupts from
these bits are masked with MSK.
GL Channel Requests: High-order bits (17-24)
of the GL requests are interpreted directly as re-
quests to the corresponding 8 channels (0-7) of the
MBD, with channel 7 highest priority and channel 0
D. File Registers
Each of the 8 channels of the MBD has 2 banks
of 7 registers (all 16-bit registers) to control
the operation of each channel (14 registers per
channel). The Channel Control Latch (CCL) determines
which set of file registers (which channel) is
active. Selection of banks is made by the appro-
priate ConTRoL (CTRL) function in a normal instruc-
tion. Normal operation is through the registers of
bank 0, which is selected by any EXIT operation (so
that each interrupt begins in bankO); the registers
of bank 1 are available for auxiliary operation.
Five of t.e registers are nominally assigned specific
purposes, but only the CTR is restricted to specific
functions; all may be specified as the SouRCe (SRC)
or DeSTination (DST) of a normal instruction.
1. CTR: ConTrol Register.
Contains status bits and the program address
in Control Memory (CM) for interrupts and addressing
the CM by normal instructions. Bits 0-11 of the
CTR may be loaded directly from the Instruction
Register (IR) by an LCI instruction as well as
being specified as the SRC or DST of a normal
Bits 0-11: Program address in CM used by normal
instructions with CM as SRC or DST or by Jump Via
CTR (JVC) instruction to begin processing an inter-
rupt at the specified address; high-order bits are
ignored for CM less than 4096 words.
Bits 12-15: Status bits which may be set and tested
by MBD instructions.
2. ILR: Instruction List Register.
List pointer which contains the address of the
next word in the list of instructions stored In the
computer memory; used to transfer instructions from
the computer memory to the MBD processor.
3. DAR: Data Address Register.
List pointer which contains the address of the
list of data stored in computer mnory, used to
transfer data between the MBD and computer memory.
4. WCR: Word Count Register.
Contains the running word count of the number
of words to be transferred in a block transfer of
5. CCR: CAMAC Command Register.
CAMAC CNAF command as for the BAR with 16 bits,
not including FS.
6. GPl: General Purpose Register Number 1.
For general use.
7. GP2: General Purpose Register Number 2.
For general use. Note that the. 7 auxiliary
registers in bank 1 can be used as additional gen-
eral--purpose registers (though addressed as specific
file registers). The CTR in bank I functions in
the same way as the CTR in bank 0.
E. MBD Registers
A number of special-purpose registers- are
addressable in whcle or in part by the MBD
1. CM: Control Memory.
Nominally 1024 words (minimum 256, maximum
4096) of 16-bit memory containing program instruc-
tions and data for MBD operations. Addressable
either by the STOre (STO) and WaD (LOD) instruc-
tions or as the SouRCe (SRC) or DeSTination (DST)
of a normal instruction.
2. IR: Instruction Register.
16-bit register which contains the instruction
to be executed by the MBD. The IR may be loaded
from the computer CPU by loading the LIR, after
which the instruction is executed in single-cyale
mode. In normal run-mode operation, the IR is
loaded automatically in sequence from the address
in the CM specified by the Program Counter (PCR).
3. ATR: AriThmetic Register.
16-bit register which contains the result of
the last normal operation; its value is included as
a source in many of the normal instruction opera-
tions. The SHiFt (SHF) instruction operates
directly on the ATR without using the arithmetic
logic unit of the MBD processor, so that the tests_
for zero and carry are not valid, though the test
for negative is. For all other instructions the
Here’s what’s next.
This report can be searched. Note: Results may vary based on the legibility of text within the document.
Tools / Downloads
Get a copy of this page or view the extracted text.
Citing and Sharing
Basic information for referencing this web page. We also provide extended guidance on usage rights, references, copying or embedding.
Reference the current page of this Report.
Bevington, P.R. PROGRAMMER'S GUIDE TO THE MICROPROGRAMMED BRANCH DRIVER FOR THE PDP-11., report, January 1, 1972; New Mexico. (https://digital.library.unt.edu/ark:/67531/metadc1027729/m1/5/: accessed May 19, 2019), University of North Texas Libraries, Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.