PROGRAMMER'S GUIDE TO THE MICROPROGRAMMED BRANCH DRIVER FOR THE PDP-11. Page: 4 of 16
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instruction increments the PCR to point to location
1, and it therefore assumes the PCR has been pre-
viously reset to 0 by a Reset MBD instruction from
the computer CPU or by an EXIT instruction in the
Bits 4-5: Extended Memory - not yet documented.
Bit 6: Interrupt Enable - enables the program in-
terrupt (at priority BR5 with vectors starting at
location 400 in computer memory) to the computer
CPU for the 25 interrupts of the MBD (0 - disable,
1 - enable). The highest priority (at the highest
location in computer memory 540-543) Is the branch
or bus error, which is identifiable with bits 13
and 14 of the CSR; the next 8 interrupts are from
XEQ INT commands from the 8 MBD channels; and the
lowest priority interrupts are the low-order 16 bits
of the Graded-Lam Requests (GLR) masked by the MASK
Bit 7: Ready - status of MBD (bit 1) or initialized
channel (bit 2); note that bit 7 is easily testable
by byte tests for sign.
Bits 8-10: Channel Select - selects which of 8
channels to initialize by bit 2.
Bit 13: Branch Error - a branch time-out error
will generate an interrupt identifiable by this bit.
Bit 14: Bus Error - a UNIBUS transfer time-out
error will generate an interrupt identifiable by
2. PDR: Program Data Register; DA 764002,
Used to transfer data or instructions between
the computer CPU and the MBD registers or Control
3. MSK: MaSK for GLR interrupts; DA 764004,
Used to mask (AND) the low-order bits (1-16)
of the Graded Lam (GL) interrupt requests (GLR). A
bit a 1 will enable an interrupt at the correspond-
4. LIR: Load Instruction Register; DA 764006,
Used to load the Instruction Register (IR) of
the MBD from the computer CPU and execute the in-
struction. When the LIR is loaded, the contents
are transferred to the IR and the instruction is
executed; the mode should be single-cycle for proper
B. DMA Registers
Two 16-bit registers are addressable only by
the MBD but control the flow of information on the
1. MAR: Memory Address Register.
Contains the address in computer memory for
Direct Memory Access (DMA) transfers. This address
is a wcrd address, whereas addresses transferred
from PDP-11 programs are generally byte addresses
and must be divided by two (or shifted right one
2. MDR: Memory Data Register.
Contains the data of the last DMA transfer
from memory or the next transfer to computer memory.
C. CAMAC Registers
Three registers are addressable by the MBD and
control communication between the MBD and the CAMAC
crates and modules.
1. BAR: Branch Address Register; 16 bits
decoded into 21 bits.
Used to specify the Crate, Number, Address,
and Function (CHAF) command for CAMAC operation.
Bite 0-3: Address (A) or register within module;
transferred as 4 bits BAl, 2, 4, 8 to CAMAC.
Bits 4-8: Number (N) of module within crate;
transferred as 5 bits BN1, 2, 4, 8, 16 to CAMAC.
Bits 9-11: Crate number (C) between 1 and 7; de-
coded to one bit of 7 bits BCR1-BCR7 for CAMAC with
one bit per crate.
Bits 12-15: Function (F) to be performed, not in-
cluding F8, which is specified by the control
(CTRL) portion of the Instruction Register (IR) by
BRN (F8 - 0) or BRC (F8 - 1); decoded into 5 bits
BF1, 2, 4, 8, 16, including F8, to CAMAC.
2. BDR and BDB: Branch Data Resister; 24-
bit register divided into two parts for manipulation
by 16-bit processor.
BDR: Low-order bits (1-16) of CAMAC data.
BDH: High-order bits (17-24) of CAMAC data.
3. GLR: Graded L's Register: 24-bit resis-
ter of which only the low-order portion is addrees-
able by the MBD.
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Bevington, P.R. PROGRAMMER'S GUIDE TO THE MICROPROGRAMMED BRANCH DRIVER FOR THE PDP-11., report, January 1, 1972; New Mexico. (https://digital.library.unt.edu/ark:/67531/metadc1027729/m1/4/: accessed April 23, 2019), University of North Texas Libraries, Digital Library, https://digital.library.unt.edu; crediting UNT Libraries Government Documents Department.