Oak Ridge National Laboratory Instrumentation and Controls Division Annual Progress Report: 1958 Page: 1

                                
INSTRUMENTATION AND CONTROLS DIVISION
ANNUAL PROGRESS REPORT
DECIMAL PRINTOUT FOR 256-CHANNEL PJLSE-HEIGHT ANALYZER
N. W. Hill
In magnetic-core multichannel analyzers employing binary logic for
the address or channel number generation, "locked-in" printout in the
decimal form for each address requires binary-to-decimal conversion.
Since this conversion necessitates a large number of components and fur-
ther manipulation to make it compatible with present printout machines,
either decimal printout of the channel number has been avoided entirely
or an auxiliary decimal scaler has been employed to count serially each
pulse used to advance the address scaler during the printout operation.
In this scheme it is relatively easy for one scaler to get out of step
with the other. Such a system is usually referred to as a "non-locked-
in" address readout and requires complete reliability in both scalers
for the readout address number to be meaningful.
One printout method now in use on a 256-channel pulse-height ana-
lyzer at the Bulk Shielding Facility which does have a semi-locked-in
feature is a binary-to-octal conversion of the six least significant
binary stages of the address scaler. This readout system requires a
minimum of components and has proved reliable, but its octal code is not
readily interpreted by the inexperienced. Further, since the address
scaler is not completely decoded, there is still some doubt as to the
actual address of the channel being read out.
Another method that does have a completely "locked-in" feature has
been in use at the Bulk Shielding Facility for six months. This system
achieves binary-to-decimal conversion by use of a ferrite core plane with
22 special sense windings, sense amplifiers, and three modified Hewlett-
Packard AC-4A decade scaling units. The address current drive lines to
this plane in the analyzer memory are identical with the drive lines of
a normal memory plane; each time a particular core in a normal plane is
selected by the full switching current, the core occupying this same po-
sition in the special plane is also selected. As its selection is
uniquely determined by one of the 256 possible combinations of the eight
binary stages of the address scaler, a decimal number from 0 to 255 can
be assigned to the core. Since there is no inhibit winding in this plane,
a selected core during a memory cycle goes through two reversals of mag-
netic state, inducing two current pulses on any sense winding threading
this core. As is indicated in Table 1, these pulses suitably amplified
are used to set the proper decimal numbers into the three decade scalers.
The AC-4A decade scaling units used generate an analog stairstep
voltage designed for use with the Hewlett-Packard model 560A digital re-
corder. With suitable programing of the pulse-height analyzer and dig-
ital recorder, this method furnishes a completely synchronized printout
regardless of the sequence in which the channel readout occurs. For in-
stance, at low counting rates (limited by printer speed of 4 lines/sec)