Thermal annealing behavior of an oxide layer under silicon

Thermal annealing behavior of an oxide layer under silicon

Date: December 15, 1982
Creator: Hamdi, A. H.; McDaniel, Floyd Del. (Floyd Delbert), 1942-; Pinizzotto, Russell F.; Matteson, Samuel E.; Lam, H. W. & Malhi, S. D. S.
Description: This article discusses the thermal annealing behavior of an oxide layer under silicon.
Contributing Partner: UNT College of Arts and Sciences
Charge Collection Studies on Integrated Circuit Test Structures using Heavy-Ion Microbeams and MEDICI Simulation Calculations

Charge Collection Studies on Integrated Circuit Test Structures using Heavy-Ion Microbeams and MEDICI Simulation Calculations

Date: May 2000
Creator: Guo, Baonian
Description: Ion induced charge collection dynamics within Integrated Circuits (ICs) is important due to the presence of ionizing radiation in the IC environment. As the charge signals defining data states are reduced by voltage and area scaling, the semiconductor device will naturally have a higher susceptibility to ionizing radiation induced effects. The ionizing radiation can lead to the undesired generation and migration of charge within an IC. This can alter, for example, the memory state of a bit, and thereby produce what is called a "soft" error, or Single Event Upset (SEU). Therefore, the response of ICs to natural radiation is of great concern for the reliability of future devices. Immunity to soft errors is listed as a requirement in the 1997 National Technology Roadmap for Semiconductors prepared by the Semiconductor Industry Association in the United States. To design more robust devices, it is essential to create and test accurate models of induced charge collection and transport in semiconductor devices. A heavy ion microbeam produced by an accelerator is an ideal tool to study charge collection processes in ICs and to locate the weak nodes and structures for improvement through hardening design. In this dissertation, the Ion Beam Induced Charge Collection ...
Contributing Partner: UNT Libraries
Real-Time Systems: An Introduction and the State-of-the-Art

Real-Time Systems: An Introduction and the State-of-the-Art

Date: March 16, 2009
Creator: Kavi, Krishna M.; Akl, Robert G. & Hurson, Ali
Description: This encyclopedia article gives an overview of the broad area of real-time systems. This task is daunting because real-time systems are everywhere, and yet no generally accepted definition differentiates real-time systems from non-real-time systems.
Contributing Partner: UNT College of Engineering
A Materials Approach to Silicon Wafer Level Contamination Issues from the Wet Clean Process

A Materials Approach to Silicon Wafer Level Contamination Issues from the Wet Clean Process

Date: December 1996
Creator: Hall, Lindsey H. (Lindsey Harrison)
Description: Semiconductor devices are built using hyperpure silicon and very controlled levels of doping to create desired electrical properties. Contamination can alter these precisely controlled electrical properties that can render the device non-functional or unreliable. It is desirable to determine what impurities impact the device and control them. This study consists of four parts: a) determination of acceptable SCI (Standard Clean 1) bath contamination levels using VPD-DSE-GFAAS (Vapor Phase Decomposition Droplet Surface Etching Graphite Furnace Atomic Absorption Spectroscopy), b) copper deposition from various aqueous HF solutions, c) anion contamination from fluoropolymers used in chemical handling and d) metallic contamination from fluoropolymers and polyethylene used in chemical handling. A technique was developed for the determination of metals on a silicon wafer source at low levels. These levels were then correlated to contamination levels in a SCI bath. This correlation permits the determination of maximum permissible solution contaminant levels. Copper contamination is a concern for depositing on the wafer surface from hydrofluoric acid solutions. The relationship between copper concentration on the wafer surface and hydrofluoric acid concentration was determined. An inverse relationship exists and was explained by differences in diffusion rates between the differing copper species existing in aqueous hydrofluoric acid solutions. Finally, ...
Contributing Partner: UNT Libraries
An Efficient Hybrid Heuristic and Probabilistic Model for the Gate Matrix Layout Problem in VLSI Design

An Efficient Hybrid Heuristic and Probabilistic Model for the Gate Matrix Layout Problem in VLSI Design

Date: August 1993
Creator: Bagchi, Tanuj
Description: None
Contributing Partner: UNT Libraries
An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design

An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design

Date: August 2014
Creator: Battina, Brahmasree
Description: Integrated Circuits (ICs) have a broad range of applications in healthcare, military, consumer electronics etc. The acronym VLSI stands for Very Large Scale Integration and is a process of making ICs by placing millions of transistors on a single chip. Because of advancements in VLSI design technologies, ICs are getting smaller, faster in speed and more efficient, making personal devices handy, and with more features. In this thesis work an interactive framework is designed in which the fundamental concepts of digital logic design and VLSI design such as logic gates, MOS transistors, combinational and sequential logic circuits, and memory are presented in a simple, interactive and user friendly way to create interest in students towards engineering fields, especially Electrical Engineering and Computer Engineering. Most of the concepts are explained in this framework by taking the examples which we see in our daily lives. Some of the critical design concerns such as power and performance are presented in an interactive way to make sure that students can understand these significant concepts in an easy and user friendly way.
Contributing Partner: UNT Libraries