Date: September 29, 1998
Creator: Aton, T.J.; Bouanani, M. E.; Doyle, B.L.; Duggan, J.L.; Guo, B.N.; McDaniel, F.D. et al.
Description: As feature sizes of Integrated Circuits (ICs) continue to shrinlL the sensitivity of these devices, particularly SRAMS and DR4Ms, to natural radiation is increasing. The radiation can lead to the uncontrolled deposition of charge within an IC, which ean alter, for example, the memoty state of a bit and thereby produce what is edled a `SOW error, or Single Event Upset (SEU). The response of ICS to natural background radiation is therefore of great coneem regarding the reliability of Mure devices. In this paper, we present results where Ion Beam Induced Charge Collection (TBICC) technique was used to simulate neutron-induced Si recoil dlkcts in IC test structures. The present wo~ wnducted at the San& National Laboratories, uses a 10 MeV Carbon mierobeam with 1 pm spot to scan test structures on specifically designed ICS. The test structure contains junctions typical of S RAMS and DRAMs. Charge is eolleeted from different areas of the IC under various conditions of junction back bias. The data are digitized and displayed as 3D images combined with KY) coordination. With the aid of IC layout informatio~ the 3D images are sepamted into difTerent layers to allow the identification of charge collection etlciency in the test ...
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