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A New N-way Reconfigurable Data Cache Architecture for Embedded Systems

Description: Performance and power consumption are most important issues while designing embedded systems. Several studies have shown that cache memory consumes about 50% of the total power in these systems. Thus, the architecture of the cache governs both performance and power usage of embedded systems. A new N-way reconfigurable data cache is proposed especially for embedded systems. This thesis explores the issues and design considerations involved in designing a reconfigurable cache. The proposed reconf… more
Date: December 2009
Creator: Bani, Ruchi Rastogi
Item Type: Refine your search to only Thesis or Dissertation
open access

FPGA Implementation of Low Density Party Check Codes Decoder

Description: Reliable communication over the noisy channel has become one of the major concerns in the field of digital wireless communications. The low density parity check codes (LDPC) has gained lot of attention recently because of their excellent error-correcting capacity. It was first proposed by Robert G. Gallager in 1960. LDPC codes belong to the class of linear block codes. Near capacity performance is achievable on a large collection of data transmission and storage.In my thesis I have focused on h… more
Date: August 2009
Creator: Vijayakumar, Suresh
Item Type: Refine your search to only Thesis or Dissertation
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