A Dual Dielectric Approach for Performance Aware Reduction of Gate Leakage in Combinational Circuits
Description:
Design of systems in the low-end nanometer domain has introduced new dimensions in power consumption and dissipation in CMOS devices. With continued and aggressive scaling, using low thickness SiO2 for the transistor gates, gate leakage due to gate oxide direct tunneling current has emerged as the major component of leakage in the CMOS circuits. Therefore, providing a solution to the issue of gate oxide leakage has become one of the key concerns in achieving low power and high performance CMOS …
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Date:
May 2006
Creator:
Mukherjee, Valmiki