Design and Optimization of Components in a 45nm CMOS Phase Locked Loop
Description:
A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and di…
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Date:
December 2006
Creator:
Sarivisetti, Gayathri
Partner:
UNT Libraries