WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays

Description:

This presentation accompanies a paper discussing research on a novel scheme to reduce static leakage energy in SRAM arrays.

Creator(s):
Creation Date: February 2004
Partner(s):
UNT College of Engineering
Collection(s):
UNT Scholarly Works
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Total Uses: 32
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Creator (Author):
Gomathisankaran, Mahadevan

University of North Texas; Iowa State University

Creator (Author):
Tyagi, Akhilesh

Iowa State University

Date(s):
  • Creation: February 2004
Description:

This presentation accompanies a paper discussing research on a novel scheme to reduce static leakage energy in SRAM arrays.

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Note:

Abstract: The increasing sub-threshold leakage current levels with newer technology nodes have been identified by ITRS (2001) as one of the major fundamental problems faced by the semiconductor industry. Concurrently, the expected performance improvement and functionality integration expectations drive the continued reduction in feature size. This results in ever-increasing power per unit area and the accompanying problem of heat removal and cooling as stated in J.M.C. Stork (1995). Portable battery-powered applications, fuelled by pervasive and embedded computing, have seen tremendous growth and have reached a point where battery energy and power density can't be increased further according to T. Bell (1991). This raises the computational throughput per watt target for the future technology nodes. SRAM arrays which are used widely as a system component, such as caches and register files, in both high-performance and portable systems, are getting to be dominant power consumers because of their large capacity and area. Hence any reduction in cache energy can result in considerable overall power reduction. The authors propose a novel circuit technique using depletion mode devices, to reduce the static energy of SRAM array in an on-chip by 90% without any performance impact.

Physical Description:

22 p.

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Subject(s):
Keyword(s): logic arrays | static leakage energy | caches
Source: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2004, Lafayette, Louisiana, United States
Contributor(s):
Partner:
UNT College of Engineering
Collection:
UNT Scholarly Works
Identifier:
  • ARK: ark:/67531/metadc96819
Resource Type: Presentation
Format: Image
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Access: Public