Efficient Energy Saving Scheme for On-Chip Caches

Description:

This paper discusses efficient energy saving techniques for on-chip caches, focusing especially on drowsy cache schemes.

Creator(s):
Creation Date: 2002
Partner(s):
UNT College of Engineering
Collection(s):
UNT Scholarly Works
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Creator (Author):
Gomathisankaran, Mahadevan

University of North Texas; Iowa State University

Creator (Author):
Somani, Arun

Iowa State University

Date(s):
  • Creation: 2002
Description:

This paper discusses efficient energy saving techniques for on-chip caches, focusing especially on drowsy cache schemes.

Degree:
Note:

Abstract: With the reduction in feature size the static power component, such as the leakage power, dominates the dynamic power consumption in the on-chip caches. It has been observed that all cache lines need not be kept alive at all times. Only a very few lines during a given window of time need to be actively powered from the footprint, i.e., they are accessed during that time. Earlier research has addressed the issue of how to determine the set of active lines and how long to keep them active (powered). Circuit techniques have also been developed to keep a cache line in low leakage state i.e., Drowsy State when the line is not being accessed or used. Such a cache is called drowsy cache. These circuit techniques try to achieve maximum reduction in the leakage power without losing the information content and with minimal performance penalty associated with power transitions. These techniques when used with optimal switching scheme, which decides when and what lines to drowse, results in maximum reduction in energy consumed. In this paper, the authors study the cache access pattern to evaluate them and arrive at an optimal scheme to implement the drowsy cache. The authors achieve energy reduction on the average of 88% of maximum gain achievable through the underlying circuit technique. The authors also compare the performance of their scheme with the earlier proposed schemes and show that the authors can achieve up to 6% of higher saving in cache energy for the benchmarks studied (with an average on 4% for all benchmarks with equal weights) without any additional performance penalty.

Physical Description:

10 p.

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Subject(s):
Keyword(s): on-chip cache | leakage | energy
Partner:
UNT College of Engineering
Collection:
UNT Scholarly Works
Identifier:
  • ARK: ark:/67531/metadc94293
Resource Type: Paper
Format: Text
Rights:
Access: Public