Advanced Technology for Source Drain Resistance Reduction in Nanoscale FinFETs

Description:

Dual gate MOSFET structures such as FinFETs are widely regarded as the most promising option for continued scaling of silicon based transistors after 2010. This work examines key process modules that enable reduction of both device area and fin width beyond requirements for the 16nm node. Because aggressively scaled FinFET structures suffer significantly degraded device performance due to large source/drain series resistance (RS/D), several methods to mitigate RS/D such as maximizing contact area, silicide engineering, and epitaxially raised S/D have been evaluated.

Creator(s): Smith, Casey Eben
Creation Date: May 2008
Partner(s):
UNT Libraries
Collection(s):
UNT Theses and Dissertations
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Total Uses: 2,958
Past 30 days: 131
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Creator (Author):
Publisher Info:
Publisher Name: University of North Texas
Place of Publication: Denton, Texas
Date(s):
  • Creation: May 2008
  • Digitized: September 15, 2008
Description:

Dual gate MOSFET structures such as FinFETs are widely regarded as the most promising option for continued scaling of silicon based transistors after 2010. This work examines key process modules that enable reduction of both device area and fin width beyond requirements for the 16nm node. Because aggressively scaled FinFET structures suffer significantly degraded device performance due to large source/drain series resistance (RS/D), several methods to mitigate RS/D such as maximizing contact area, silicide engineering, and epitaxially raised S/D have been evaluated.

Degree:
Level: Doctoral
Language(s):
Subject(s):
Keyword(s): FinFET | nanoscale | resistance
Contributor(s):
Partner:
UNT Libraries
Collection:
UNT Theses and Dissertations
Identifier:
  • OCLC: 263871783 |
  • ARK: ark:/67531/metadc6052
Resource Type: Thesis or Dissertation
Format: Text
Rights:
Access: Public
License: Copyright
Holder: Smith, Casey Eben
Statement: Copyright is held by the author, unless otherwise noted. All rights reserved.