Modeling and reduction of gate leakage during behavioral synthesis of nanoscale CMOS circuits.

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Description:

The major sources of power dissipation in a nanometer CMOS circuit are capacitive switching, short-circuit current, static leakage and gate oxide tunneling. However, with the aggressive scaling of technology the gate oxide direct tunneling current (gate leakage) is emerging as a prominent component of power dissipation. For sub-65 nm CMOS technology where the gate oxide (SiO2) thickness is very low, the direct tunneling current is the major form of tunneling. There are two contribution parts in this thesis: analytical modeling of behavioral level components for direct tunneling current and propagation delay, and the reduction of tunneling current during behavioral synthesis. Gate oxides of multiple thicknesses are useful in reducing the gate leakage dissipation. Analytical models from first principles to calculate the tunneling current and the propagation delay of behavioral level components is presented, which are backed by BSIM4/5 models and SPICE simulations. These components are characterized for 45 nm technology and an algorithm is provided for scheduling of datapath operations such that the overall tunneling current dissipation of a datapath circuit under design is minimal. It is observed that the oxide thickness that is being considered is very low it may not remain constant during the course of fabrication. Hence the algorithm takes process variation into consideration. Extensive experiments are conducted for various behavioral level benchmarks under various constraints and observed significant reductions, as high as 75.3% (with an average of 64.3%).

Creator(s): Velagapudi, Ramakrishna
Creation Date: May 2006
Partner(s):
UNT Libraries
Collection(s):
UNT Theses and Dissertations
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Total Uses: 109
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Publisher Info:
Publisher Name: University of North Texas
Place of Publication: Denton, Texas
Date(s):
  • Creation: May 2006
  • Digitized: April 22, 2008
Description:

The major sources of power dissipation in a nanometer CMOS circuit are capacitive switching, short-circuit current, static leakage and gate oxide tunneling. However, with the aggressive scaling of technology the gate oxide direct tunneling current (gate leakage) is emerging as a prominent component of power dissipation. For sub-65 nm CMOS technology where the gate oxide (SiO2) thickness is very low, the direct tunneling current is the major form of tunneling. There are two contribution parts in this thesis: analytical modeling of behavioral level components for direct tunneling current and propagation delay, and the reduction of tunneling current during behavioral synthesis. Gate oxides of multiple thicknesses are useful in reducing the gate leakage dissipation. Analytical models from first principles to calculate the tunneling current and the propagation delay of behavioral level components is presented, which are backed by BSIM4/5 models and SPICE simulations. These components are characterized for 45 nm technology and an algorithm is provided for scheduling of datapath operations such that the overall tunneling current dissipation of a datapath circuit under design is minimal. It is observed that the oxide thickness that is being considered is very low it may not remain constant during the course of fabrication. Hence the algorithm takes process variation into consideration. Extensive experiments are conducted for various behavioral level benchmarks under various constraints and observed significant reductions, as high as 75.3% (with an average of 64.3%).

Degree:
Level: Master's
Language(s):
Subject(s):
Keyword(s): high level synthesis | gate leakage current | power minimization
Contributor(s):
Partner:
UNT Libraries
Collection:
UNT Theses and Dissertations
Identifier:
  • OCLC: 71211934 |
  • ARK: ark:/67531/metadc5590
Resource Type: Thesis or Dissertation
Format: Text
Rights:
Access: Use restricted to UNT Community (strictly enforced)
License: Copyright
Holder: Velagapudi, Ramakrishna
Statement: Copyright is held by the author, unless otherwise noted. All rights reserved.