Design and Optimization of Components in a 45nm CMOS Phase Locked Loop

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Description:

A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a systematic optimization of each of its components, and an analog and mixed signal behavioral design approach have been implemented using cadence custom IC design tools.

Creator(s): Sarivisetti, Gayathri
Creation Date: December 2006
Partner(s):
UNT Libraries
Collection(s):
UNT Theses and Dissertations
Usage:
Total Uses: 320
Past 30 days: 20
Yesterday: 1
Creator (Author):
Publisher Info:
Publisher Name: University of North Texas
Place of Publication: Denton, Texas
Date(s):
  • Creation: December 2006
  • Digitized: April 11, 2008
Description:

A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a systematic optimization of each of its components, and an analog and mixed signal behavioral design approach have been implemented using cadence custom IC design tools.

Degree:
Level: Master's
Language(s):
Subject(s):
Keyword(s): CMOS | phase locked loop | voltage controlled oscillator | mixed signal analysis | nano technology
Contributor(s):
Partner:
UNT Libraries
Collection:
UNT Theses and Dissertations
Identifier:
  • OCLC: 138320516 |
  • ARK: ark:/67531/metadc5397
Resource Type: Thesis or Dissertation
Format: Text
Rights:
Access: Use restricted to UNT Community
License: Copyright
Holder: Sarivisetti, Gayathri
Statement: Copyright is held by the author, unless otherwise noted. All rights reserved.