This system will be undergoing maintenance Tuesday, September 30, 2014 from 9:00 AM to 2:00 PM CDT.

A New N-way Reconfigurable Data Cache Architecture for Embedded Systems

Access: Use of this item is restricted to the UNT Community
Description:

Performance and power consumption are most important issues while designing embedded systems. Several studies have shown that cache memory consumes about 50% of the total power in these systems. Thus, the architecture of the cache governs both performance and power usage of embedded systems. A new N-way reconfigurable data cache is proposed especially for embedded systems. This thesis explores the issues and design considerations involved in designing a reconfigurable cache. The proposed reconfigurable data cache architecture can be configured as direct-mapped, two-way, or four-way set associative using a mode selector. The module has been designed and simulated in Xilinx ISE 9.1i and ModelSim SE 6.3e using the Verilog hardware description language.

Creator(s): Bani, Ruchi Rastogi
Creation Date: December 2009
Partner(s):
UNT Libraries
Collection(s):
UNT Theses and Dissertations
Usage:
Total Uses: 138
Past 30 days: 1
Yesterday: 0
Creator (Author):
Publisher Info:
Publisher Name: University of North Texas
Place of Publication: Denton, Texas
Date(s):
  • Creation: December 2009
Description:

Performance and power consumption are most important issues while designing embedded systems. Several studies have shown that cache memory consumes about 50% of the total power in these systems. Thus, the architecture of the cache governs both performance and power usage of embedded systems. A new N-way reconfigurable data cache is proposed especially for embedded systems. This thesis explores the issues and design considerations involved in designing a reconfigurable cache. The proposed reconfigurable data cache architecture can be configured as direct-mapped, two-way, or four-way set associative using a mode selector. The module has been designed and simulated in Xilinx ISE 9.1i and ModelSim SE 6.3e using the Verilog hardware description language.

Degree:
Level: Master's
Note:

Restricted until 1 January 2015

Language(s):
Subject(s):
Keyword(s): Reconfigurable architecture | embedded systems | data cache memory
Contributor(s):
Partner:
UNT Libraries
Collection:
UNT Theses and Dissertations
Identifier:
  • OCLC: 588876429 |
  • UNTCAT: b3824822 |
  • ARK: ark:/67531/metadc12079
Resource Type: Thesis or Dissertation
Format: Text
Rights:
Access: Use restricted to UNT Community
License: Copyright
Holder: Bani, Ruchi Rastogi
Statement: Copyright is held by the author, unless otherwise noted. All rights reserved.