A Verilog 8051 Soft Core for FPGA Applications Page: 15
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Reset outputs from ctr
Prog. Counter = 0000h
Operand Reg [7:0] = 00h
PSW = 00h
CPU STATE = CS 0
EXE STATE = EX 0
rom addr = 12'b0
rom rd = O
ram addr = 00h
ram out data =00h
ram out-bit = 0
ram out bit addr
=0
xrm addr =0000h
xrm out data = 00h
xrm rd/ wr = 0
aluop_code =00h
alu src I = 00h
alu src 2 = 00h
alu src 3 = 00h
alusrccy = 0
alu src ac = 0Yes
Reset memory control
rom addr = 12'b0 ram addr = 00h
rom rd = 0 ram out data =00h
xrm addr =0000h ram out-bit = 0
xrm out data = 00h ram out bit addr=0
xrm rd/wr = 0I dec_op_out = op_reg1
Figure 4.1-4: Overview of Controller Program Flow15
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Rangoonwala, Sakina. A Verilog 8051 Soft Core for FPGA Applications, thesis, August 2009; Denton, Texas. (https://digital.library.unt.edu/ark:/67531/metadc11013/m1/25/: accessed April 25, 2024), University of North Texas Libraries, UNT Digital Library, https://digital.library.unt.edu; .