Exploration Of Energy And Area Efficient Techniques For Coarse-grained Reconfigurable Fabrics

Description:

Coarse-grained fabrics are comprised of multi-bit configurable logic blocks and configurable interconnect. This work is focused on area and energy optimization techniques for coarse-grained reconfigurable fabric architectures. In this work, a variety of design techniques have been explored to improve the utilization of computational resources and increase energy savings. This includes splitting, folding, multi-level vertical interconnect. In addition to this, I have also studied fully connected homogeneous and heterogeneous architectures, and 3D architecture. I have also examined some of the hybrid strategies of computation unit’s arrangements. In order to perform energy and area analysis, I selected a set of signal and image processing benchmarks from MediaBench suite. I implemented various fabric architectures on 90nm ASIC process from Synopsys. Results show area improvement with energy savings as compared to baseline architecture.

Creator(s): Yadav, Anil
Creation Date: December 2011
Partner(s):
UNT Libraries
Collection(s):
UNT Theses and Dissertations
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Total Uses: 54
Past 30 days: 5
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Publisher Info:
Publisher Name: University of North Texas
Publisher Info: www.unt.edu
Place of Publication: Denton, Texas
Date(s):
  • Creation: December 2011
Description:

Coarse-grained fabrics are comprised of multi-bit configurable logic blocks and configurable interconnect. This work is focused on area and energy optimization techniques for coarse-grained reconfigurable fabric architectures. In this work, a variety of design techniques have been explored to improve the utilization of computational resources and increase energy savings. This includes splitting, folding, multi-level vertical interconnect. In addition to this, I have also studied fully connected homogeneous and heterogeneous architectures, and 3D architecture. I have also examined some of the hybrid strategies of computation unit’s arrangements. In order to perform energy and area analysis, I selected a set of signal and image processing benchmarks from MediaBench suite. I implemented various fabric architectures on 90nm ASIC process from Synopsys. Results show area improvement with energy savings as compared to baseline architecture.

Degree:
Level: Master's
PublicationType: Thesi
Language(s):
Subject(s):
Keyword(s): Domain-specific reconfigurable factrics | low energy designs | area-efficient | coarse-grained fabrics
Contributor(s):
Partner:
UNT Libraries
Collection:
UNT Theses and Dissertations
Identifier:
  • ARK: ark:/67531/metadc103413
Resource Type: Thesis or Dissertation
Format: Text
Rights:
Access: Public
Holder: Yadav, Anil
License: Copyright
Statement: Copyright is held by the author, unless otherwise noted. All rights Reserved.