Hardware Implementation Of Conditional Motion Estimation In Video Coding

Description:

This thesis presents the rate distortion analysis of conditional motion estimation, a process in which motion computation is restricted to only active pixels in the video. We model active pixels as independent and identically distributed Gaussian process and inactive pixels as Gaussian-Markov process and derive the rate distortion function based on conditional motion estimation. Rate-Distortion curves for the conditional motion estimation scheme are also presented. In addition this thesis also presents the hardware implementation of a block based motion estimation algorithm. Block matching algorithms are difficult to implement on FPGA chip due to its complexity. We implement 2D-Logarithmic search algorithm to estimate the motion vectors for the image. The matching criterion used in the algorithm is Sum of Absolute Differences (SAD). VHDL code for the motion estimation algorithm is verified using ISim and is implemented using Xilinx ISE Design tool. Synthesis results for the algorithm are also presented.

Creator(s): Kakarala, Avinash
Creation Date: December 2011
Partner(s):
UNT Libraries
Collection(s):
UNT Theses and Dissertations
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Publisher Info:
Publisher Name: University of North Texas
Publisher Info: www.unt.edu
Place of Publication: Denton, Texas
Date(s):
  • Creation: December 2011
Description:

This thesis presents the rate distortion analysis of conditional motion estimation, a process in which motion computation is restricted to only active pixels in the video. We model active pixels as independent and identically distributed Gaussian process and inactive pixels as Gaussian-Markov process and derive the rate distortion function based on conditional motion estimation. Rate-Distortion curves for the conditional motion estimation scheme are also presented. In addition this thesis also presents the hardware implementation of a block based motion estimation algorithm. Block matching algorithms are difficult to implement on FPGA chip due to its complexity. We implement 2D-Logarithmic search algorithm to estimate the motion vectors for the image. The matching criterion used in the algorithm is Sum of Absolute Differences (SAD). VHDL code for the motion estimation algorithm is verified using ISim and is implemented using Xilinx ISE Design tool. Synthesis results for the algorithm are also presented.

Degree:
Level: Master's
PublicationType: Thesi
Language(s):
Subject(s):
Keyword(s): Rate distortion analysis | conditional motion estimation | 2D-logarithmic search algorithm
Contributor(s):
Partner:
UNT Libraries
Collection:
UNT Theses and Dissertations
Identifier:
  • ARK: ark:/67531/metadc103341
Resource Type: Thesis or Dissertation
Format: Text
Rights:
Access: Public
Holder: Kakarala, Avinash
License: Copyright
Statement: Copyright is held by the author, unless otherwise noted. All rights Reserved.